Abstract: A two stage latch or shift register latch with very reduced propagation delay in the second stage, that may be used for LSSD type integrated circuits. The two stage register includes a first stage receiving and latching data. The first stage may also include a scan input for scanning in test data. The data is passed to a second stage which provides the received data as an output and latches the output. The preferred second stage includes a pair of cross coupled inverters, and a complementary clock stage. The complementary clock stage selectively passes the received data from the first stage to the output and, then, the second latch latches the output.