Patents by Inventor Masaaki Anezaki

Masaaki Anezaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6693341
    Abstract: When an element isolation film is formed by the LOCOS technique, as an underlying buffer layer of an oxidation resisting film, a pad oxidation film and pad poly-Si film are used. When an element is formed, they are used as a gate oxide film and a part of a gate electrode to relax a level difference between the gate electrode and the wiring on the element isolation film. A first poly-Si film (pad poly-Si film) is etched to leave its certain thickness to relax the level difference more greatly. In such a process, in manufacturing a semiconductor integrated circuit using the LOCOS technique, the number of manufacturing steps can be reduced and the level difference between the gate electrode on the gate insulating film and the wiring on the element isolation film can be relaxed.
    Type: Grant
    Filed: November 7, 2002
    Date of Patent: February 17, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Nobuyuki Sekikawa, Wataru Andoh, Masaaki Anezaki, Masaaki Momen
  • Publication number: 20030062587
    Abstract: When an element isolation film is formed by the LOCOS technique, as an underlying buffer layer of an oxidation resisting film, a pad oxidation film and pad poly-Si film are used. When an element is formed, they are used as a gate oxide film and a part of a gate electrode to relax a level difference between the gate electrode and the wiring on the element isolation film. A first poly-Si film (pad poly-Si film) is etched to leave its certain thickness to relax the level difference more greatly. In such a process, in manufacturing a semiconductor integrated circuit using the LOCOS technique, the number of manufacturing steps can be reduced and the level difference between the gate electrode on the gate insulating film and the wiring on the element isolation film can be relaxed.
    Type: Application
    Filed: November 7, 2002
    Publication date: April 3, 2003
    Applicant: Sanyo Electric Co., Ltd., a Japan corporation
    Inventors: Nobuyuki Sekikawa, Wataru Andoh, Masaaki Anezaki, Masaaki Momen
  • Patent number: 6489661
    Abstract: When an element isolation film is formed by the LOCOS technique, as an underlying buffer layer of an oxidation resisting film, a pad oxidation film and pad poly-Si film are used. When an element is formed, they are used as a gate oxide film and a part of a gate electrode to relax a level difference between the gate electrode and the wiring on the element isolation film. A first poly-Si film (pad poly-Si film) is etched to leave its certain thickness to relax the level difference more greatly. In such a process, in manufacturing a semiconductor integrated circuit using the LOCOS technique, the number of manufacturing steps can be reduced and the level difference between the gate electrode on the gate insulating film and the wiring on the element isolation film can be relaxed.
    Type: Grant
    Filed: February 15, 2001
    Date of Patent: December 3, 2002
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Nobuyuki Sekikawa, Wataru Andoh, Masaaki Anezaki, Masaaki Momen
  • Publication number: 20010029093
    Abstract: When an element isolation film is formed by the LOCOS technique, as-an underlying buffer layer of an oxidation resisting film, a pad oxidation film and pad poly-Si film are used. When an element is formed, they are used as a gate oxide film and a part of a gate electrode to relax a level difference between the gate electrode and the wiring on the element isolation film. A first poly-Si film (pad poly-Si film) is etched to leave its certain thickness to relax the level difference more greatly. In such a process, in manufacturing a semiconductor integrated circuit using the LOCOS technique, the number of manufacturing steps can be reduced and the level difference between the gate electrode on the gate insulating film and the wiring on the element isolation film can be relaxed.
    Type: Application
    Filed: February 15, 2001
    Publication date: October 11, 2001
    Applicant: Sanyo Electric Co., Ltd., a Japan Corporation
    Inventors: Nobuyuki Sekikawa, Wataru Andoh, Masaaki Anezaki, Masaaki Momen
  • Patent number: 6211046
    Abstract: When an element isolation film is formed by the LOCOS technique, as an underlying buffer layer of an oxidation resisting film, a pad oxidation film and pad poly-Si film are used. When an element is formed, they are used as a gate oxide film and a part of a gate electrode to relax a level difference between the gate electrode and the wiring on the element isolation film. A first poly-Si film (pad poly-Si film) is etched to leave its certain thickness to relax the level difference more greatly. In such a process, in manufacturing a semiconductor integrated circuit using the LOCOS technique, the number of manufacturing steps can be reduced and the level difference between the gate electrode on the gate insulating film and the wiring on the element isolation film can be relaxed.
    Type: Grant
    Filed: July 27, 1999
    Date of Patent: April 3, 2001
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Nobuyuki Sekikawa, Wataru Andoh, Masaaki Anezaki, Masaaki Momen