Patents by Inventor Masaaki Aoki

Masaaki Aoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4949145
    Abstract: In a homo-junction bipolar transistor suitable for a low temperature operation below 200.degree.K. (particularly below 77 K), the maximum value of the impurity concentration of an intrinsic base region is set to be at least 1.times.10.sup.18 /cm.sup.3. The impurity concentration of an emitter region is set to a value lower than this maximum value. Thus, a base resistance can be reduced and high speed operation becomes possible. Furthermore, bandgap narrowing develops in the intrinsic base region and a common-emitter current gain in the low temperature operation can be kept at a sufficient value. When this homo-junction bipolar transistor is formed together with complementary insulated gate field effect transistors on the surface of a semiconductor substrate, there can be obtained a Bi-CMOS device capable of a high speed operation even in the low temperature operation.
    Type: Grant
    Filed: October 4, 1988
    Date of Patent: August 14, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Yano, Masaaki Aoki, Toshiaki Masuhara, Katsuhiro Shimohigashi
  • Patent number: 4884111
    Abstract: A pair of superconducting electrodes are so formed as to interpose a smeiconductor therebetween, and a control electrode is formed on the seimiconductor through an insulator film so as to control the superconductive weak coupling state in the semiconductor between the superconducting electrodes. The distance between the superconducting electrodes is determined by the thickness of the superconductor interposed between the two electrodes, whereby the interelectrode distance is settled with a high precision to improve the uniformity of the device characteristic.And in an arrangement where two superconducting electrodes are formed on a semiconductor layer and the superconductive weak coupling state between such two electrodes is controlled by a third electrode, the gain is increadable by furnishing a varied impurity distribution in the semiconductor layer.
    Type: Grant
    Filed: July 13, 1987
    Date of Patent: November 28, 1989
    Inventors: Toshikazu Nishino, Mutsuko Miyake, Ushio Kawabe, Yutaka Harada, Masaaki Aoki, Mikio Hirano
  • Patent number: 4880869
    Abstract: This invention relates to .beta.-amino-.beta.-propiolactam derivativatives, moisture curable polyurethane compositions and their applications.The products of this invention have excellent characteristics such as good storage stability, rapid curing with atmospheric moisture and freedom from foaming.More particularly, condensed compounds are obtained by reacting specific secondary diamines such as piperazine and 1,3-(4,4'-dipiperidyl)propane with monoaldehyde having at least 3 carbon atoms, for example, isobutylaldehyde and .beta.-phenylpropylaldehyde. The .beta.-amino-.beta.-propiolactam derivatives are prepared by reacting the condensed compounds with monoisocyanate such as phenyl isocyanate and equimolar reaction products of diisocyanate with lower monohydric alcohol.In addition, the moisture curable polyurethane compositions contain said derivatives and polyisocyanate and/or polyurethane prepolymer having terminal isocyanato radicals.
    Type: Grant
    Filed: September 14, 1988
    Date of Patent: November 14, 1989
    Assignee: Mitsui Toatsu Chemicals, Inc.
    Inventors: Masaaki Aoki, Mayumi Tani, Masayuki Kamiyama, Kiyotsugu Asai
  • Patent number: 4864382
    Abstract: A MOS memory is formed in a semiconductor bulk, whereas a barrier semiconductor layer is disposed at the boundary between a MOS memory portion and the semiconductor bulk in order to reduce the effect of undesirable carriers excited by .alpha.-particles. The barrier semiconductor layer is designed to permit operation of the memory at low temperature while reducing the incidence of soft errors due to .alpha.-particles.
    Type: Grant
    Filed: January 25, 1988
    Date of Patent: September 5, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Masaaki Aoki, Kazuo Yano, Toshiaki Masuhara
  • Patent number: 4768076
    Abstract: A CMOS IC is formed on a semiconductor crystalline surface having a plane azimuth (110) or (023), or of a plane azimuth close thereto (plane azimuth substantially in parallel with the above-mentioned planes), in order to increase the speed of operation.At low temperatures, dependency of the carrier mobility upon the plane azimuth becomes more conspicuous as shown in FIG. 1, and the difference of mobility is amplified depending upon the planes. Therefore, employment of the above-mentioned crystalline planes helps produce a great effect when the CMOS device is to be operated at low temperature (e.g., 100.degree. K. or lower), and helps operate the device at high speeds.
    Type: Grant
    Filed: September 11, 1985
    Date of Patent: August 30, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Masaaki Aoki, Toshiaki Masuhara, Terunori Warabisako, Shoji Hanamura, Yoshio Sakai, Seiichi Isomae, Satoshi Meguro, Shuji Ikeda
  • Patent number: 4710648
    Abstract: Electric charge is supplied to a circuit node being in a charge storing state within a signal processor in response to a signal-processing commencing signal. The processor is operated in a low-temperature range, for example, in the range of temperature below 200K. By this structure, a leakage current is reduced, a high degree of integration equivalent to that of a dynamic circuit can be obtained, and the simplicity of a static circuit not requiring any complicated internal/external timing signals can be realized.
    Type: Grant
    Filed: May 6, 1985
    Date of Patent: December 1, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Shoji Hanamura, Masaaki Aoki, Toshiaki Masuhara
  • Patent number: 4435962
    Abstract: A refrigerating apparatus including a first compressor, a condenser, a first pressure reducer a first evaporator, a second pressure reducer and a second evaporator connected together by lines to form a refrigerating circuit for a refrigerant to flow therethrough, wherein a second compressor is connected at its suction side to the second pressure reducer for receiving gaseous component of refrigerant from the first evaporator and connected at its discharge side to the line between the first compressor and the condenser. An evaporative pressure control valve may be mounted in the line between the first evaporator and the second pressure reducer or the line between the second pressure reducer and the second evaporator. A bypass line mounting an electromagnetic valve may connect the line between the first evaporator and the second pressure reducer to the line between the second pressure reducer and the second evaporator.
    Type: Grant
    Filed: June 22, 1981
    Date of Patent: March 13, 1984
    Assignees: Shin Meiwa Industry Co., Ltd., Hitachi, Ltd.
    Inventors: Taketoshi Mochizuki, Kazuya Matsuo, Mituo Kudo, Akira Arai, Junichi Yamada, Keizi Shono, Masaaki Aoki, Masaichi Ohmori, Genichiro Nishi
  • Patent number: 4280131
    Abstract: A planar-type pleochroic light emitting diode and a method of fabricating the same are disclosed, the diode allowing from a single chip a plurality of light emissions having different center wavelengths. Impurity diffusion is carried out by use of a film having a masking effect to an impurity and a different film partially non-uniform in thickness having no masking effect to the impurity to form a plurality of diffusion regions having different depths. The diode has excellent coupling with an optical fiber, can be easily fabricated and is suitable for use in optical multiplex communication.
    Type: Grant
    Filed: March 7, 1979
    Date of Patent: July 21, 1981
    Assignee: Hitachi, Ltd.
    Inventors: Yuichi Ono, Kazuhiro Ito, Mitsuhiro Mori, Masaaki Aoki, Kazuhiro Kurata
  • Patent number: 4183039
    Abstract: A light emitting semiconductor device wherein a p-n junction is defined by a ditch and wherein the ditch either extends to a low resistance layer or is away from the low resistance layer at most 1/2 of the width of the ditch is disclosed. It has the merit that the near field pattern is much more uniform than in a prior-art device.
    Type: Grant
    Filed: June 6, 1978
    Date of Patent: January 8, 1980
    Assignee: Hitachi, Ltd.
    Inventors: Masaaki Aoki, Yuichi Ono, Makoto Morioka, Kazuhiro Ito, Mitshiuro Mori, Kazuhiro Kurata