Abstract: An image sensing apparatus including a plurality of pixels arranged in a row direction and a column direction. Each pixel including a first photoelectric conversion element, a second photoelectric conversion element. A processing unit including a first capacitor and a second capacitor which are configured to hold a signal obtained by a signal of the first photoelectric conversion element and a signal of the second photoelectric conversion element. In a first image sensing mode, the processing unit holds an image sensing signal obtained by adding the signal of the first photoelectric conversion element and the signal of the second photoelectric conversion element in the second capacitor. In a second image sensing mode, the processing unit holds the added image sensing signal in a combined capacitance obtained by connecting the first capacitor and the second capacitor in parallel.

Abstract: A solid-state imaging apparatus including a pixel array, the column signal lines, arranged so as to correspond to each column of the pixel array, for reading out signals from the pixel array, the current sources, for supplying currents corresponding to potentials of controlling terminals of the current sources to the column signal lines, and a supplying unit for supplying a first potential and a second potential to the controlling terminals, wherein in a first mode for reading out the signals from the pixel array, the supplying unit supplies the first potential to the controlling terminals, and in a second mode for stopping the reading out, the supplying unit supplies the second potential to the controlling terminals, and the currents supplied by the current sources of the second mode is smaller than that of the first mode.

Abstract: It is an object of the present invention to provide a solid-state imaging apparatus that outputs digital signals at high speed. A solid-state imaging apparatus is provided that includes plural analog-to-digital converters that convert analog signals obtained by photoelectric conversion into digital signals, plural digital memories that store the digital signals converted by the analog-to-digital converters, plural block digital output lines that are provided to correspond to blocks of the plural digital memories and to which the digital signals stored in the plural digital memories included in the blocks are output, a common digital output line that outputs the digital signals output from the plural block digital output lines, buffer circuits that buffer the digital signals output from the block digital output lines, and block selecting units that can switch the block digital output lines electrically connected to the common digital output line.

Abstract: An image sensor includes a pixel unit having first and second photoelectric converters, an amplifier provided commonly for the first and second photoelectric converters, first and second transfer transistors configured to respectively transfer charges generated in the first and second electric converters to an input portion of the amplifier. The signal read out by the readout portion includes a first optical signal read out in a state in which charges are transferred from the first photoelectric converter to the input portion by the first transfer transistor, and a second optical signal read out, after the readout of the first optical signal, in a state in which charges are transferred from the second photoelectric converter to the input portion by the second transfer transistor.

Abstract: An apparatus includes a pixel array in which pixels for outputting an analog signal are arranged in a matrix, vertical output lines each of which is connected to pixels in a same column, A/D conversion units, which are individually connected to the vertical output lines, for converting the analog signal into a digital signal, and a constant current supply unit for supplying a constant current to the A/D conversion units. Each of the A/D conversion units includes an integration unit for integrating the constant current, a comparison unit for comparing the integrated constant current with the analog signal and outputting a comparison signal, and a digital signal storage unit for storing a digital signal corresponding to the comparison signal. The integration unit includes an input capacitor for receiving the constant current. The comparison unit is connected to the constant current supply unit via the input capacitor.

Abstract: A pulse edge selection circuit includes an input stage which selects and passes one clock from among a plurality of clocks and an output stage which outputs the clock to an edge detection circuit. The output stage has a combination of a plurality of NOR gates and a plurality of NAND gates, which are connected alternately, both the NOR gates and NAND gates having a plurality of input terminals. If the edge detection circuit is a type which detects falling edges of clocks and generates a pulse which rises on the falling edge of a first clock and falls on the falling edge of a second clock, a NOR gate is used as an output gate which outputs the first clock and the second clock. On the other hand, if a pulse is generated on rising edges, a NAND gate is used as an output gate.

Abstract: A solid-state image pickup apparatus includes a pixel area in which pixels each having at least a photoelectric conversion unit and an amplification transistor for amplifying and outputting a signal of the photoelectric conversion unit are two-dimensionally arranged in horizontal and vertical directions, wherein a power supply wiring, which extends in a vertical direction along pixel boundaries of horizontal and vertical directions while meandering, is arranged on one of two pixel lines adjoining to each other in the horizontal direction in the pixel area, and the power supply wiring is connected to one of a source and a drain of the amplification transistor on each of the two pixel lines. Thus, it is possible to provide a high-sensitivity and high-image-quality amplified solid-state image pickup apparatus in which a difference of sensitivities at one-line intervals is small.

Abstract: A solid-state image sensor has a pixel array including pixel units and column signal lines. Each pixel unit includes a photoelectric converter and an amplifier transistor which outputs a signal to the column signal line. The sensor includes a cascode current source which supplies a current to the amplifier transistor and which includes cascode-connected first and second transistors, a first bias circuit which determines a voltage of a first node connected to a gate of the first transistor, and a second bias circuit which determines a voltage of a second node connected to a gate of the second transistor.

Abstract: It is an object of the present invention to provide a solid-state imaging apparatus that outputs digital signals at high speed. A solid-state imaging apparatus is provided that includes plural analog-to-digital converters that convert analog signals obtained by photoelectric conversion into digital signals, plural digital memories that store the digital signals converted by the analog-to-digital converters, plural block digital output lines that are provided to correspond to blocks of the plural digital memories and to which the digital signals stored in the plural digital memories included in the blocks are output, a common digital output line that outputs the digital signals output from the plural block digital output lines, buffer circuits that buffer the digital signals output from the block digital output lines, and block selecting units that can switch the block digital output lines electrically connected to the common digital output line.

Abstract: It is disclosed that, as an embodiment, a test circuit includes a test signal supply unit configured to supply a test signal via a signal line to signal receiving units provided in a plurality of columns, wherein the test signal supply unit is a voltage buffer or a current buffer, and the test circuit has a plurality of test signal supply units and a plurality of signal lines, and wherein at least one test signal supply unit is electrically connected to one signal line different from a signal line to which another test signal supply unit is electrically connected.

Abstract: A photoelectric conversion apparatus includes a plurality of photoelectric conversion elements configured to convert incident light to electric carriers, an amplifier MOS transistor shared by the plurality of photoelectric conversion elements, a plurality of floating diffusions connected to the gate electrode of the amplifier MOS transistor, and a plurality of transfer MOS transistors arranged corresponding to the respective photoelectric conversion elements, each of the transfer MOS transistors transferring electric carriers from corresponding one of the photoelectric conversion elements to corresponding one of the floating diffusions. In such a photoelectric conversion apparatus, at least two of the floating diffusions are electrically connected to each other with a wiring line included in the same wiring layer as the gate electrode of the amplifier MOS transistor.

Abstract: In a photoelectric conversion device, a first metal wiring layer and a second metal wiring layer are arranged on a semiconductor substrate that includes a pixel region where a plurality of pixels are arrayed in a matrix, each pixel including at least a photoelectric conversion portion and an amplification transistor. The second metal wiring layer includes power supply lines each configured to supply a power supply voltage to the amplification transistors of at least two pixel columns, and the amplification transistor of a pixel column having no power supply line receives the power supply voltage from the power supply line via the first metal wiring layer.

Abstract: A delay locked loop circuit comprising a VCDL which outputs a feedback clock by delaying an input clock in accordance with a magnitude of a control voltage, a phase comparator which detects a phase difference between the feedback clock and a reference clock by comparing the feedback clock with the reference clock, and outputs an Up-signal for raising the control voltage and a Down-signal for lowering the control voltage in accordance with the phase difference, a control voltage generation circuit which determines the control voltage in accordance with the Up-signal and the Down-signal, and outputs the control voltage to the VCDL, and a reset circuit which resets the phase comparator based on a logical OR between the reference clock and a first intermediate clock which is a signal obtained by delaying the input clock by the VCDL and is output before the feedback clock.

Abstract: An image sensing device includes a multilayer wiring structure comprising a first wiring layer and a second wiring layer. The second wiring layer comprises a plurality of vertical signal lines extending in the vertical direction among a plurality of photoelectric conversion units of a pixel unit to transfer the signal output by an amplification transistor and a plurality of vertical power supply lines extending in the vertical direction between two pixel units adjacent to each other in the horizontal direction to supply a power supply voltage to the amplification transistor or the reset transistor. The vertical power supply lines supply the power supply voltage to the reset transistor of the adjacent pixel unit on a first side in the horizontal direction and supply the power supply voltage to the amplification transistor of the adjacent pixel unit on a second side in the horizontal direction.

Abstract: A photoelectric conversion apparatus includes a plurality of photoelectric conversion elements configured to convert incident light to electric carriers, an amplifier MOS transistor shared by the plurality of photoelectric conversion elements, a plurality of floating diffusions connected to the gate electrode of the amplifier MOS transistor, and a plurality of transfer MOS transistors arranged corresponding to the respective photoelectric conversion elements, each of the transfer MOS transistors transferring electric carriers from corresponding one of the photoelectric conversion elements to corresponding one of the floating diffusions. In such a photoelectric conversion apparatus, at least two of the floating diffusions are electrically connected to each other with a wiring line included in the same wiring layer as the gate electrode of the amplifier MOS transistor.

Abstract: A pulse edge selection circuit includes an input stage which selects and passes one clock from among a plurality of clocks and an output stage which outputs the clock to an edge detection circuit. The output stage has a combination of a plurality of NOR gates and a plurality of NAND gates, which are connected alternately, both the NOR gates and NAND gates having a plurality of input terminals. If the edge detection circuit is a type which detects falling edges of clocks and generates a pulse which rises on the falling edge of a first clock and falls on the falling edge of a second clock, a NOR gate is used as an output gate which outputs the first clock and the second clock. On the other hand, if a pulse is generated on rising edges, a NAND gate is used as an output gate.

Abstract: A photoelectric conversion apparatus includes a plurality of photoelectric conversion elements configured to convert incident light to electric carriers, an amplifier MOS transistor shared by the plurality of photoelectric conversion elements, a plurality of floating diffusions connected to the gate electrode of the amplifier MOS transistor, and a plurality of transfer MOS transistors arranged corresponding to the respective photoelectric conversion elements, each of the transfer MOS transistors transferring electric carriers from corresponding one of the photoelectric conversion elements to corresponding one of the floating diffusions. In such a photoelectric conversion apparatus, at least two of the floating diffusions are electrically connected to each other with a wiring line included in the same wiring layer as the gate electrode of the amplifier MOS transistor.

Abstract: A delay locked loop circuit comprising a VCDL which outputs a feedback clock by delaying an input clock in accordance with a magnitude of a control voltage, a phase comparator which detects a phase difference between the feedback clock and a reference clock by comparing the feedback clock with the reference clock, and outputs an Up-signal for raising the control voltage and a Down-signal for lowering the control voltage in accordance with the phase difference, a control voltage generation circuit which determines the control voltage in accordance with the Up-signal and the Down-signal, and outputs the control voltage to the VCDL, and a reset circuit which resets the phase comparator based on a logical OR between the reference clock and a first intermediate clock which is a signal obtained by delaying the input clock by the VCDL and is output before the feedback clock.

Abstract: The invention provides a solid-state image pickup apparatus which comprises a pixel area in which pixels each having at least a photoelectric conversion unit and an amplification transistor for amplifying and outputting a signal of the photoelectric conversion unit are two-dimensionally arranged in horizontal and vertical directions, wherein a power supply wiring, which extends in a vertical direction along pixel boundaries of horizontal and vertical directions while meandering, is arranged on one of two pixel lines adjoining to each other in the horizontal direction in the pixel area, and the power supply wiring is connected to one of a source and a drain of the amplification transistor on each of the two pixel lines. Thus, it is possible to provide a high-sensitivity and high-image-quality amplified solid-state image pickup apparatus in which a difference of sensitivities at one-line intervals is small.

Abstract: It is an object of the present invention to provide a solid-state imaging apparatus that outputs digital signals at high speed. A solid-state imaging apparatus is provided that includes plural analog-to-digital converters that convert analog signals obtained by photoelectric conversion into digital signals, plural digital memories that store the digital signals converted by the analog-to-digital converters, plural block digital output lines that are provided to correspond to blocks of the plural digital memories and to which the digital signals stored in the plural digital memories included in the blocks are output, a common digital output line that outputs the digital signals output from the plural block digital output lines, buffer circuits that buffer the digital signals output from the block digital output lines, and block selecting units that can switch the block digital output lines electrically connected to the common digital output line.