Abstract: To provide an oven controlled crystal oscillator which can keep constant the temperature of a quartz resonator housed within a thermostatic oven, thereby ensuring stable operation of the quartz resonator. An oven controlled crystal oscillator has a control system for exercising control so that the temperature of a quartz resonator becomes a target temperature Ttarg of a predetermined fixed value. The quartz resonator is housed within a thermostatic oven which is configured to compare a set temperature Tr and a measured temperature Tic based on an outside air temperature measured by a temperature sensor and which is controlled so that a difference between both temperatures is narrowed. The quartz resonator has characteristics influenced by an environmental temperature.

Abstract: To provide an oven controlled crystal oscillator which can keep constant the temperature of a quartz resonator housed within a thermostatic oven, thereby ensuring stable operation of the quartz resonator. An oven controlled crystal oscillator has a control system for exercising control so that the temperature of a quartz resonator becomes a target temperature Ttarg of a predetermined fixed value. The quartz resonator is housed within a thermostatic oven which is configured to compare a set temperature Tr and a measured temperature Tic based on an outside air temperature measured by a temperature sensor and which is controlled so that a difference between both temperatures is narrowed. The quartz resonator has characteristics influenced by an environmental temperature.

Abstract: Each of varicaps 50A to 50C configured to be connected in parallel is an MOS capacitor III produced under a common and single process condition. Each of the varicaps 50A to 50C has a conductor layer serving as a second electrode and formed via a capacitance insulating film on a first conductivity-type semiconductor substrate serving as a first electrode, and a second conductivity-type impurity region formed near a surface in proximity to a region of the first conductivity-type semiconductor substrate opposing the conductor layer. Each of the varicaps 50A to 50C is configured such that a capacitance value as a capacitance element between the first conductivity-type semiconductor substrate serving as the first electrode and the conductor layer serving as the second electrode is changed by applying a control voltage to the conductor layer while applying any one of a plurality of types of direct-current voltages having different voltages to the second conductivity-type impurity region.

Abstract: Each of varicaps 50A to 50C configured to be connected in parallel is an MOS capacitor III produced under a common and single process condition. Each of the varicaps 50A to 50C has a conductor layer serving as a second electrode and formed via a capacitance insulating film on a first conductivity-type semiconductor substrate serving as a first electrode, and a second conductivity-type impurity region formed near a surface in proximity to a region of the first conductivity-type semiconductor substrate opposing the conductor layer. Each of the varicaps 50A to 50C is configured such that a capacitance value as a capacitance element between the first conductivity-type semiconductor substrate serving as the first electrode and the conductor layer serving as the second electrode is changed by applying a control voltage to the conductor layer while applying any one of a plurality of types of direct-current voltages having different voltages to the second conductivity-type impurity region.

Abstract: A reference potential converter circuit comprises: a first resistor (resistance value R1) serving as a feedback resistor for an operational amplifier; a second resistor (resistance value R2) connected to the first resistor and a reference voltage; and a third resistor (reference value R3) and a fourth resistor (reference value R4) connected between a power supply and ground. A difference voltage between Vout and Vref is divided by an R1/R2 ratio and applied to an inverting input terminal of the operational amplifier. A power supply voltage is divided by an R3/R4 ratio and applied to a non-inverting input terminal of the operational amplifier. The R1/R2 ratio and the R3/R4 ratio are equal.

Abstract: A voltage regulator comprises an N type depletion MOS transistor having a drain connected to the positive electrode side of a power supply, a source connected to a stabilizing capacitor, and a gate receiving a constant reference voltage, and has an output terminal at the source of the N type depletion MOS transistor. In this simple circuit configuration, the voltage regulator can markedly reduce a noise carried on an output voltage.

Abstract: A nonvolatile memory cell includes: a first NMOS transistor having a floating gate; a second NMOS transistor and a third NMOS transistor connected to a drain side and a source side of the first NMOS transistor; and a first PMOS transistor and a second PMOS transistor each having the floating gate as a gate, and wherein a read signal is inputted to gates of the second and third NMOS transistors, a control gate signal is inputted to a source and an n-well of the first PMOS transistor, an erase signal is inputted to a source and an n-well of the second PMOS transistor, and a write data signal is inputted to a source of the first NMOS transistor.

Abstract: A nonvolatile memory cell, comprising: a first NMOS transistor having a floating gate; a second NMOS transistor and a third NMOS transistor connected to a drain side and a source side of the first NMOS transistor; and a first PMOS transistor and a second PMOS transistor each having the floating gate as a gate, and wherein a read signal is inputted to gates of the second and third NMOS transistors, a control gate signal is inputted to a source and an n-well of the first PMOS transistor, an erase signal is inputted to a source and an n-well of the second PMOS transistor, and a write data signal is inputted to a source of the first NMOS transistor.

Abstract: An AC amplifier has an amplification circuit, and a bias circuit connected together by connecting wiring. The bias circuit receives an input of an AC signal from the amplification circuit via the connecting wiring. A DC voltage of the bias circuit conformed to the amplitude of the AC signal of the amplification circuit is supplied to the amplification circuit via the connecting wiring.

Abstract: A bypass capacitance is connected to a node between first and second self-bias resistances connected in series between an input and an output of an inverter. The bypass capacitance accommodates changes in the output voltage of the inverter to suppress the feedback effect from the output side to the input side of the inverter. That is, the bypass capacitance plays the role of suppressing a decrease in the input impedance by the Miller effect.

Abstract: An AC amplifier has an amplification circuit, and a bias circuit connected together by connecting wiring. The bias circuit receives an input of an AC signal from the amplification circuit via the connecting wiring. A DC voltage of the bias circuit conformed to the amplitude of the AC signal of the amplification circuit is supplied to the amplification circuit via the connecting wiring.

Abstract: A bypass capacitance is connected to a node between first and second self-bias resistances connected in series between an input and an output of an inverter. The bypass capacitance accommodates changes in the output voltage of the inverter to suppress the feedback effect from the output side to the input side of the inverter. That is, the bypass capacitance plays the role of suppressing a decrease in the input impedance by the Miller effect.

Abstract: A semiconductor device including multiple high-voltage drive transistors in its output section is improved in electrostatic withstand voltage by connecting electrostatic protection transistors in parallel with the high-voltage drive transistors connected to the output pads. The drain withstand voltage of the electrostatic protection transistors is made lower than the drain withstand voltage of the high-voltage drive transistors. In addition, the channel length of electrostatic protection transistors is made short to enable efficient bipolar operation of the electrostatic protection transistors.

Abstract: A MOS-type capacitor includes a semiconductor substrate of a first conductive type serving as a first electrode, a conductor layer formed on the semiconductor substrate via a capacitive insulation film and serving as a second electrode, and an impurity region of a second conductive type formed in the vicinity of the surface of the semiconductor substrate at a location in proximity to a region facing the conductor layer. The MOS-type capacitor is used as a variable capacitor in a VCO (voltage-controlled oscillator) having a widened frequency range.

Abstract: A semiconductor device including multiple high-voltage drive transistors in its output section is improved in electrostatic withstand voltage by connecting electrostatic protection transistors in parallel with the high-voltage drive transistors connected to the output pads. The drain withstand voltage of the electrostatic protection transistors is made lower than the drain withstand voltage of the high-voltage drive transistors. In addition, the channel length of electrostatic protection transistors is made short to enable efficient bipolar operation of the electrostatic protection transistors.

Abstract: A semiconductor device including multiple high-voltage drive transistors in its output section is improved in electrostatic withstand voltage by connecting electrostatic protection transistors in parallel with the high-voltage drive transistors connected to the output pads. The drain withstand voltage of the electrostatic protection transistors is made lower than the drain withstand voltage of the high-voltage drive transistors. In addition, the channel length of electrostatic protection transistors is made short to enable efficient bipolar operation of the electrostatic protection transistors.

Abstract: To provide a semiconductor substrate and a light-valve semiconductor substrate capable of preventing the threshold value of a MOS transistor on a single-crystal silicon device forming layer from increasing and forming a MOS integrated circuit with a high reliability even for a long-time operation. A semiconductor substrate and a light-valve semiconductor substrate comprising a single-crystal silicon thin-film device forming layer 5001 formed above an insulating substrate 5004 through an adhesive layer 5003 and an insulating layer 5002 formed on the single-crystal silicon thin-film device forming layer, wherein a heat conductive layers 5201 and 5202 made of a material with a high heat conductivity are arranged between the single-crystal silicon thin-film device forming layer and the adhesive layer and on the insulating layer.

Abstract: In a method of manufacturing a semiconductor chip, a wire is traveled in one way to cut a wafer into a plurality of chips while a wire train where wires are arranged by pitches of scribe lines is brought into contact with the scribe lines of the wafer linearly, and an abrasive solution is supplied to a contact portion thereof.

Abstract: A light valve has a composite substrate comprised of an electrically insulating substrate and a semiconductor single crystal thin film formed over the electrically insulating substrate. A pixel array comprising semiconductor switch elements is formed in the semiconductor single crystal thin film. A peripheral circuit having circuit elements is formed in the semiconductor single crystal thin film so that a small-sized, high speed light valve is obtained. X- driver and Y-driver circuits are formed in the semiconductor single crystal thin film and controlled by a control circuit, such as a video signal processing circuit, which receives and processes video signals inputted directly from an external source. The peripheral circuit can be a DRAM sense amplifier for sensing charges stored in each pixel of the pixel array to detect defects in the pixel array.

Abstract: The invention provides a semi-conductor light valve device and a process for fabricating the same. The device comprises a composite substrate having a supporte substrate, a light-shielding thin film formed on said supporte substrate and semiconductive thin film disposed on the light-shielding thin film with interposing an insulating thin film. A switching element made of a transistor and a transparent electrode for driving light valve are formed on the semiconductive thin film, and the switching element and the transparent electrode are connected electrically with each other. The transistor includes a channel region in the semiconductive thin film and a main gate electrode for controlling the conduction in the channel region, and the light-shielding thin film layer is so formed as to cover the channel region on the side opposite to said channel region, so as to prevent effectively a back channel and shut off the incident light.