Patents by Inventor Masaaki KANAZAWA
Masaaki KANAZAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11924985Abstract: A display device includes a display panel that includes a first hole and a device housing that is configured such that the display panel is fastened and fixed to the device housing by a screw passed through the first hole and screwed into the screw hole. The display panel includes a display-side positioning part which is configured to fit to a portion of the device housing to perform positioning of the display panel with respect to the device housing and which includes the first hole, and the device housing includes a housing-side positioning part which is configured to fit to the display-side positioning part to perform the positioning and which includes a second hole formed so as to communicate with the first hole when the housing-side positioning part is fitted to the display-side positioning part.Type: GrantFiled: October 6, 2022Date of Patent: March 5, 2024Assignee: YAZAKI CORPORATIONInventors: Junichi Ikumi, Masaaki Sano, Naoki Ueno, Akira Masuda, Takahiro Shimada, Takeshi Iwamoto, Shota Kosuga, Ryuta Suzuki, Satoru Kanazawa, Junnosuke Nishimura
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Patent number: 10978308Abstract: method of manufacturing a semiconductor device capable of manufacturing a miniaturized semiconductor device is provided. The method of manufacturing a semiconductor device according to an embodiment includes the steps of: preparing a semiconductor substrate having a first surface and a second surface which is an opposite surface of the first surface; forming a hard mask having an opening on the first surface; forming a gate trench extending toward the second surface on the first surface using the hard mask as a mask; widening the width of the opening; filling the opening with an interlayer insulating film; and forming a contact hole in the interlayer insulating film by removing the hard mask.Type: GrantFiled: May 9, 2019Date of Patent: April 13, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Masaaki Kanazawa
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Publication number: 20190371614Abstract: method of manufacturing a semiconductor device capable of manufacturing a miniaturized semiconductor device is provided. The method of manufacturing a semiconductor device according to an embodiment includes the steps of: preparing a semiconductor substrate having a first surface and a second surface which is an opposite surface of the first surface; forming a hard mask having an opening on the first surface; forming a gate trench extending toward the second surface on the first surface using the hard mask as a mask; widening the width of the opening; filling the opening with an interlayer insulating film; and forming a contact hole in the interlayer insulating film by removing the hard mask.Type: ApplicationFiled: May 9, 2019Publication date: December 5, 2019Inventor: Masaaki KANAZAWA
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Patent number: 9985108Abstract: An electrode comes in ohmic contact with an AlGaN layer. A semiconductor device SD has a nitride semiconductor layer GN2, and an AlxGa(1-x)N layer AGN (hereinafter referred to as “AlGaN layer AGN), and Al electrodes DE, SE. in the AlGaN layer AGN, 0<x?0.2 is satisfied. Also, both of a concentration of a p-type impurity and a concentration of an n-type impurity in the AlGaN layer AGN are 1×1016 cm?3 or lower. In this example, the p-type impurity is exemplified by, for example, Be, C, and Mg, and the n-type impurity is exemplified by Si, S, and Se. Also, the Al electrodes DE and SE are connected to the AlGaN layer AGN. Because a composition ratio of Al is limited to the above-mentioned range, the Al electrodes DE and SE are brought into ohmic contact with the AlGaN layer AGN.Type: GrantFiled: July 14, 2014Date of Patent: May 29, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tatsuo Nakayama, Masaaki Kanazawa, Yasuhiro Okamoto, Takashi Inoue, Hironobu Miyamoto, Ryohei Nega
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Patent number: 9536978Abstract: To improve performance of a semiconductor device. For example, on the assumption that a superlattice layer is inserted between a buffer layer and a channel layer, a concentration of acceptors introduced into nitride semiconductor layers forming a part of the superlattice layer is higher than a concentration of acceptors introduced into nitride semiconductor layers forming the other part of the superlattice layer. That is, the concentration of acceptors introduced into the nitride semiconductor layers having a small band gap is higher than the concentration of acceptors introduced into the nitride semiconductor layers having a large band gap.Type: GrantFiled: March 5, 2014Date of Patent: January 3, 2017Assignee: Renesas Electronics CorporationInventors: Tatsuo Nakayama, Hironobu Miyamoto, Yasuhiro Okamoto, Ryohei Nega, Masaaki Kanazawa, Takashi Inoue
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Publication number: 20160133715Abstract: The reliability of a field effect transistor made of a nitride semiconductor material is improved. An ohmic electrode includes a plurality of unit electrodes isolated to be separated from each other. With this configuration, an on-state current can be prevented from flowing in the unit electrodes in a y-axial direction (negative direction). Further, in the respective unit electrodes, a current density of the on-state current flowing in the y-axial direction (negative direction) can be prevented from increasing. As a result, an electromigration resistance of the ohmic electrode can be improved.Type: ApplicationFiled: December 29, 2015Publication date: May 12, 2016Applicant: Renesas Electronics CorporationInventors: Yasuhiro Okamoto, Takashi Inoue, Tatsuo Nakayama, Ryohei Nega, Masaaki Kanazawa, Hironobu Miyamoto
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Patent number: 9269803Abstract: The reliability of a field effect transistor made of a nitride semiconductor material is improved. An ohmic electrode includes a plurality of unit electrodes isolated to be separated from each other. With this configuration, an on-state current can be prevented from flowing in the unit electrodes in a y-axial direction (negative direction). Further, in the respective unit electrodes, a current density of the on-state current flowing in the y-axial direction (negative direction) can be prevented from increasing. As a result, an electromigration resistance of the ohmic electrode can be improved.Type: GrantFiled: July 9, 2013Date of Patent: February 23, 2016Assignee: Renesas Electronics CorporationInventors: Yasuhiro Okamoto, Takashi Inoue, Tatsuo Nakayama, Ryohei Nega, Masaaki Kanazawa, Hironobu Miyamoto
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Publication number: 20150041821Abstract: An electrode comes in ohmic contact with an AlGaN layer. A semiconductor device SD has a nitride semiconductor layer GN2, and an AlxGa(1?x)N layer AGN (hereinafter referred to as “AlGaN layer AGN), and Al electrodes DE, SE. in the AlGaN layer AGN, 0<X?0.2 is satisfied. Also, both of a concentration of a p-type impurity and a concentration of an n-type impurity in the AlGaN layer AGN are 1×1016 cm?3 or lower. In this example, the p-type impurity is exemplified by, for example, Be, C, and Mg, and the n-type impurity is exemplified by Si, S, and Se. Also, the Al electrodes DE and SE are connected to the AlGaN layer AGN. Because a composition ratio of Al is limited to the above-mentioned range, the Al electrodes DE and SE are brought into ohmic contact with the AlGaN layer AGN.Type: ApplicationFiled: July 14, 2014Publication date: February 12, 2015Inventors: Tatsuo Nakayama, Masaaki Kanazawa, Yasuhiro Okamoto, Takashi Inoue, Hironobu Miyamoto, Ryohei Nega
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Publication number: 20140264274Abstract: To improve performance of a semiconductor device. For example, on the assumption that a superlattice layer is inserted between a buffer layer and a channel layer, a concentration of acceptors introduced into nitride semiconductor layers forming a part of the superlattice layer is higher than a concentration of acceptors introduced into nitride semiconductor layers forming the other part of the superlattice layer. That is, the concentration of acceptors introduced into the nitride semiconductor layers having a small band gap is higher than the concentration of acceptors introduced into the nitride semiconductor layers having a large band gap.Type: ApplicationFiled: March 5, 2014Publication date: September 18, 2014Applicant: Renesas Electronics CorporationInventors: Tatsuo NAKAYAMA, Hironobu MIYAMOTO, Yasuhiro OKAMOTO, Ryohei NEGA, Masaaki KANAZAWA, Takashi INOUE
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Publication number: 20140015019Abstract: The reliability of a field effect transistor made of a nitride semiconductor material is improved. An ohmic electrode includes a plurality of unit electrodes isolated to be separated from each other. With this configuration, an on-state current can be prevented from flowing in the unit electrodes in a y-axial direction (negative direction). Further, in the respective unit electrodes, a current density of the on-state current flowing in the y-axial direction (negative direction) can be prevented from increasing. As a result, an electromigration resistance of the ohmic electrode can be improved.Type: ApplicationFiled: July 9, 2013Publication date: January 16, 2014Inventors: Yasuhiro OKAMOTO, Takashi INOUE, Tatsuo NAKAYAMA, Ryohei NEGA, Masaaki KANAZAWA, Hironobu MIYAMOTO
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Publication number: 20100193862Abstract: A method of manufacturing according to the present invention includes forming a trench to a semiconductor substrate, depositing an insulating film to the trench, etching the insulating film of a bottom part of the trench by plasma etching and thereby forming to an opening part of the trench, an inclined surface at an angle of inclination a to a principal surface of the semiconductor substrate, forming a gate insulating film from a top surface of the semiconductor substrate to the insulating film of the bottom part of the trench, and forming a gate electrode on the gate insulating film.Type: ApplicationFiled: February 5, 2010Publication date: August 5, 2010Applicant: NEC ELECTRONICS CORPORATIONInventor: Masaaki KANAZAWA