Patents by Inventor Masaaki Momen
Masaaki Momen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7125787Abstract: A gate electrode includes a first polysilicon film remaining on a first oxide film, a part of a second polysilicon layer 8 superimposed on the polysilicon layer, and a part of the second polysilicon layer partially extending over second gate oxide films. Thus, the thickness of the gate electrode on the first gate oxide film is the same as that of the gate electrode of the prior art, but the film thickness t2 of the gate electrode 10 on the second gate oxide films 6A and 6B is thinner than the thickness t1 of the prior art. Therefore, the height gap h2 between the gate electrode 10 and the N+type source layer 11 and the height gap h2 between the gate electrode 10 and the N+type drain layer 12 become smaller compared to those of prior art, leading to the improved flatness of the interlayer oxide film 13.Type: GrantFiled: November 25, 2003Date of Patent: October 24, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Nobuyuki Sekikawa, Masaaki Momen, Wataru Andoh, Koichi Hirata
-
Patent number: 7045860Abstract: The semiconductor device of this invention has a P type well region formed inside a P type semiconductor substrate, on which at least three gate insulating films each having a different thickness are formed. Also, the device has the gate electrode formed extending over the three gate insulating films. The ion implantation of the impurity for controlling the threshold voltage is performed only under the thinnest gate insulating film of the three gate insulating films.Type: GrantFiled: August 9, 2002Date of Patent: May 16, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Suichi Kikuchi, Masaaki Momen
-
Patent number: 6897117Abstract: A transistor of a semiconductor device has an increased driving capacity. The semiconductor device has a first gate insulation film formed by a selective oxidation, a second gate insulation film formed by thermal oxidation and a gate electrode formed across the first and the second gate insulation films. The second gate insulation film is composed of a thicker gate insulation film and a thinner gate insulation film.Type: GrantFiled: April 5, 2004Date of Patent: May 24, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Shuichi Kikuchi, Masaaki Momen
-
Patent number: 6858489Abstract: This invention is directed to the reduction of voltage dependence and thus allows easy design of integrated semiconductor circuits. The device is equipped with a P? type resistance layer, in which a first voltage is applied to one end and a second voltage is applied to the other end and which is formed on the surface of an N-well region on the semiconductor substrate, a thin oxide film on the resistance layer, and a resistance bias electrode which includes the silicon layer formed on the thin oxide film. By adjusting the voltage applied to the resistance bias electrode, the voltage dependence of the resistance of the resistance layer is reduced.Type: GrantFiled: September 8, 2003Date of Patent: February 22, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Nobuyuki Sekikawa, Koichi Hirata, Masaaki Momen, Shinya Enomoto
-
Patent number: 6815284Abstract: A manufacturing method of this invention has an ion-implantation process for threshold voltage adjustment of an MOS transistor, including a process to form a first well of an opposite conductivity type in a substrate of one conductivity type, to form a second well of the opposite conductivity type having higher impurity concentration than that in the first well, under a region where a thin gate insulation film is formed, to form gate insulation films on the first well and the second well, each having a different thickness, to ion-implant first impurities of the one conductivity type into the wells of the opposite conductivity type under the condition that the impurities penetrate the gate insulation films of different thicknesses and to ion-implant second impurities of the one conductivity type into the second well of the opposite conductivity type under the condition that the second impurities penetrate the thin gate insulation film but do not penetrate the thick gate insulation film.Type: GrantFiled: November 27, 2002Date of Patent: November 9, 2004Assignees: Sanyo Electric Co., Ltd., Niigata Sanyo Electronics Co., Ltd.Inventors: Masafumi Uehara, Shuichi Kikuchi, Masaaki Momen
-
Publication number: 20040183145Abstract: A transistor of a semiconductor device has an increased driving capacity. The semiconductor device has a first gate insulation film formed by a selective oxidation, a second gate insulation film formed by thermal oxidation and a gate electrode formed across the first and the second gate insulation films. The second gate insulation film is composed of a thicker gate insulation film and a thinner gate insulation film.Type: ApplicationFiled: April 5, 2004Publication date: September 23, 2004Inventors: Shuichi Kikuchi, Masaaki Momen
-
Publication number: 20040113208Abstract: A gate electrode includes a first polysilicon film remaining on a first oxide film, a part of a second polysilicon layer 8 superimposed on the polysilicon layer, and a part of the second polysilicon layer partially extending over second gate oxide films. Thus, the thickness of the gate electrode on the first gate oxide film is the same as that of the gate electrode of the prior art, but the film thickness t2 of the gate electrode 10 on the second gate oxide films 6A and 6B is thinner than the thickness t1 of the prior art. Therefore, the height gap h2 between the gate electrode 10 and the N+ type source layer 11 and the height gap h2 between the gate electrode 10 and the N+ type drain layer 12 become smaller compared to those of prior art, leading to the improved flatness of the interlayer oxide film 13.Type: ApplicationFiled: November 25, 2003Publication date: June 17, 2004Applicant: Sanyo Electric Co., Ltd.Inventors: Nobuyuki Sekikawa, Masaaki Momen, Wataru Andoh, Koichi Hirata
-
Patent number: 6750518Abstract: A die size is reduced in a semiconductor device which has a gate electrode formed on a first gate insulation film and a second gate insulation film, source and drain regions (N− layers and N+ layers) formed adjacent to the gate electrode and a channel region, wherein at least the gate electrode, the channel region and the source and drain regions are polygonal in shape.Type: GrantFiled: August 9, 2002Date of Patent: June 15, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Eiji Nishibe, Suichi Kikuchi, Masaaki Momen
-
Patent number: 6737707Abstract: A transistor of a semiconductor device has an increased driving capacity. The semiconductor device has a first gate insulation film formed by a selective oxidation, a second gate insulation film formed by thermal oxidation and a gate electrode formed across the first and the second gate insulation films. The second gate insulation film is composed of a thicker gate insulation film and a thinner gate insulation film.Type: GrantFiled: August 9, 2002Date of Patent: May 18, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Shuichi Kikuchi, Masaaki Momen
-
Patent number: 6707119Abstract: A die size is reduced in a semiconductor device having a gate electrode formed on a first gate insulation film and a second gate insulation film, source and drain regions (N− layers and N+ layers) formed adjacent to the gate electrode and a channel region, wherein the gate electrode, the channel region and the source and drain regions are hexagonal. Neighboring transistors are displaced from each other by a predetermined distance.Type: GrantFiled: August 9, 2002Date of Patent: March 16, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Eiji Nishibe, Suichi Kikuchi, Masaaki Momen
-
Publication number: 20040048434Abstract: This invention is directed to the reduction of voltage dependence and thus allows easy design of integrated semiconductor circuits. The device is equipped with a P− type resistance layer, in which a first voltage is applied to one end and a second voltage is applied to the other end and which is formed on the surface of an N-well region on the semiconductor substrate, a thin oxide film on the resistance layer, and a resistance bias electrode which includes the silicon layer formed on the thin oxide film. By adjusting the voltage applied to the resistance bias electrode, the voltage dependence of the resistance of the resistance layer is reduced.Type: ApplicationFiled: September 8, 2003Publication date: March 11, 2004Applicant: Sanyo Electric Co. Ltd.Inventors: Nobuyuki Sekikawa, Koichi Hirata, Masaaki Momen, Shinya Enomoto
-
Patent number: 6693341Abstract: When an element isolation film is formed by the LOCOS technique, as an underlying buffer layer of an oxidation resisting film, a pad oxidation film and pad poly-Si film are used. When an element is formed, they are used as a gate oxide film and a part of a gate electrode to relax a level difference between the gate electrode and the wiring on the element isolation film. A first poly-Si film (pad poly-Si film) is etched to leave its certain thickness to relax the level difference more greatly. In such a process, in manufacturing a semiconductor integrated circuit using the LOCOS technique, the number of manufacturing steps can be reduced and the level difference between the gate electrode on the gate insulating film and the wiring on the element isolation film can be relaxed.Type: GrantFiled: November 7, 2002Date of Patent: February 17, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Nobuyuki Sekikawa, Wataru Andoh, Masaaki Anezaki, Masaaki Momen
-
Patent number: 6690070Abstract: A gate electrode includes a first polysilicon film remaining on a first oxide film, a part of a second polysilicon layer 8 superimposed on the polysilicon layer, and a part of the second polysilicon layer partially extending over second gate oxide films. Thus, the thickness of the gate electrode on the first gate oxide film is the same as that of the gate electrode of the prior art, but the film thickness t2 of the gate electrode 10 on the second gate oxide films 6A and 6B is thinner than the thickness t1 of the prior art. Therefore, the height gap h2 between the gate electrode 10 and the N + type source layer 11 and the height gap h2 between the gate electrode 10 and the N + type drain layer 12 become smaller compared to those of prior art, leading to the improved flatness of the interlayer oxide film 13.Type: GrantFiled: August 10, 2001Date of Patent: February 10, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Nobuyuki Sekikawa, Masaaki Momen, Wataru Andoh, Koichi Hirata
-
Patent number: 6613659Abstract: A semiconductor device having a P type well region formed inside a P type semiconductor substrate, on which at least three gate insulating films each having a different thickness are formed. Also, the device has the gate electrode formed extending over the three gate insulating films. The ion implantation of the impurity for controlling the threshold voltage is performed only under the thinnest gate insulating film of the three gate insulating films.Type: GrantFiled: August 9, 2002Date of Patent: September 2, 2003Assignee: Sanyo Electric Co., Ltd.Inventors: Suichi Kikuchi, Masaaki Momen
-
Publication number: 20030153154Abstract: A manufacturing method of this invention has an ion-implantation process for threshold voltage adjustment of an MOS transistor, including a process to form a first well of an opposite conductivity type in a substrate of one conductivity type, to form a second well of the opposite conductivity type having higher impurity concentration than that in the first well, under a region where a thin gate insulation film is formed, to form gate insulation films on the first well and the second well, each having a different thickness, to ion-implant first impurities of the one conductivity type into the wells of the opposite conductivity type under the condition that the impurities penetrate the gate insulation films of different thicknesses and to ion-implant second impurities of the one conductivity type into the second well of the opposite conductivity type under the condition that the second impurities penetrate the thin gate insulation film but do not penetrate the thick gate insulation film.Type: ApplicationFiled: November 27, 2002Publication date: August 14, 2003Applicant: Sanyo Electric Co., Ltd.Inventors: Masafumi Uehara, Shuichi Kikuchi, Masaaki Momen
-
Publication number: 20030062587Abstract: When an element isolation film is formed by the LOCOS technique, as an underlying buffer layer of an oxidation resisting film, a pad oxidation film and pad poly-Si film are used. When an element is formed, they are used as a gate oxide film and a part of a gate electrode to relax a level difference between the gate electrode and the wiring on the element isolation film. A first poly-Si film (pad poly-Si film) is etched to leave its certain thickness to relax the level difference more greatly. In such a process, in manufacturing a semiconductor integrated circuit using the LOCOS technique, the number of manufacturing steps can be reduced and the level difference between the gate electrode on the gate insulating film and the wiring on the element isolation film can be relaxed.Type: ApplicationFiled: November 7, 2002Publication date: April 3, 2003Applicant: Sanyo Electric Co., Ltd., a Japan corporationInventors: Nobuyuki Sekikawa, Wataru Andoh, Masaaki Anezaki, Masaaki Momen
-
Publication number: 20030030113Abstract: A die size is reduced in a semiconductor device having a gate electrode formed on a first gate insulation film and a second gate insulation film, source and drain regions (N− layers and N+ layers) formed adjacent to the gate electrode and a channel region, wherein the gate electrode, the channel region and the source and drain regions are hexagonal. Neighboring transistors are displaced from each other by a predetermined distance.Type: ApplicationFiled: August 9, 2002Publication date: February 13, 2003Applicant: SANYO ELECTRIC CO., LTD.Inventors: Eiji Nishibe, Suichi Kikuchi, Masaaki Momen
-
Publication number: 20030032266Abstract: The semiconductor device of this invention has a P type well region formed inside a P type semiconductor substrate, on which at least three gate insulating films each having a different thickness are formed. Also, the device has the gate electrode formed extending over the three gate insulating films. The ion implantation of the impurity for controlling the threshold voltage is performed only under the thinnest gate insulating film of the three gate insulating films.Type: ApplicationFiled: August 9, 2002Publication date: February 13, 2003Inventors: Shuichi Kikuchi, Masaaki Momen
-
Publication number: 20030030105Abstract: A die size is reduced in a semiconductor device which has a gate electrode formed on a first gate insulation film and a second gate insulation film, source and drain regions (N− layers and N+ layers) formed adjacent to the gate electrode and a channel region, wherein at least the gate electrode, the channel region and the source and drain regions are polygonal in shape.Type: ApplicationFiled: August 9, 2002Publication date: February 13, 2003Applicant: SANYO ELECTRIC CO., LTD.Inventors: Eiji Nishibe, Shuichi Kikuchi, Masaaki Momen
-
Publication number: 20030032223Abstract: A transistor of a semiconductor device has an increased driving capacity. The semiconductor device has a first gate insulation film formed by a selective oxidation, a second gate insulation film formed by thermal oxidation and a gate electrode formed across the first and the second gate insulation films. The second gate insulation film is composed of a thicker gate insulation film and a thinner gate insulation film.Type: ApplicationFiled: August 9, 2002Publication date: February 13, 2003Inventors: Shuichi Kikuchi, Masaaki Momen