Abstract: A processing system includes a first processing device and a switch device. The first processing device includes a first transmitter configured to transmit a plurality of packets, and a controller configured to acquire first time information indicating a first time at which the transmitting of the plurality of packets started. The switch device includes a first receiver configured to receive at least one of the plurality of packets transmitted from the first processing device and receive the first time information from the first processing device, a second transmitter configured to acquire second time information indicating a second time at which a link-up occurred, compare the second time information with the first time information, and perform a notification to a second processing device of occurrence of error in transmitting of the plurality of packets when the second time is later than the first time.

Abstract: A communication control device includes a plurality of inputting units to which a packet is inputted a plurality of outputting units to which the packet is outputted a selector that selects an output packet to output from an identical outputting unit among a plurality of conflict packets having the identical outputting unit as a destination, the plurality of conflict packets being selected among a plurality of packets inputted to the plurality of inputting units, based on priority information set in each conflict packet and a processing unit that updates the respective priority information of unselected packets not selected as the output packet by the selector among the plurality of conflict packets based on weighting information in accordance with a packet size.

Abstract: A processing system includes a first processing device and a switch device. The first processing device includes a first transmitter configured to transmit a plurality of packets, and a controller configured to acquire first time information indicating a first time at which the transmitting of the plurality of packets started. The switch device includes a first receiver configured to receive at least one of the plurality of packets transmitted from the first processing device and receive the first time information from the first processing device, a second transmitter configured to acquire second time information indicating a second time at which a link-up occurred, compare the second time information with the first time information, and perform a notification to a second processing device of occurrence of error in transmitting of the plurality of packets when the second time is later than the first time.

Abstract: A storage device for storing data, while compressing same value of input data, includes an input processing unit, a data storage, a first-in-first-out memory, and an output processing unit. The input processing unit is configured to, upon receiving an input value, determine whether a data value stored in the data storage at an address location corresponding to the input value is valid. If the data value is invalid, the input processing unit stores an initial value at the address location and stores the input value in the first-in-first-out memory. If the data value is valid, the input processing unit performs an arithmetic operation on the data value and stores the operation result in the address location corresponding to the input value.

Abstract: The DMA data transfer apparatus includes a memory, a communication controller, a DMA controller having a plurality of DMA engines each of which transfers data by DMA to the communication controller from the memory, and a DMA control unit. The DMA control unit determines a division size of transfer data such that the DMA engine can transfer the data, issues a data transfer directive by the DMA to the DMA controller, and controls data transfer by the DMA. The DMA control unit transmits the determination information for determination of the termination of data transfer to the communication controller. The communication controller determines the termination of data transfer based on the determination information transmitted from the DMA control unit.

Abstract: An event notifying method notifies one or a plurality of events from a device to a processor by queuing to a queue in a processor system having one or a plurality of processors. A number of non-notified events existing in the queue is managed by a counter unit, and an inconsistent state of the counter unit caused by differences in updating timings of the counter unit from the device and the processor is temporarily permitted.

Abstract: A data storing unit includes a plurality of areas divided in a predetermined range. A data writing unit writes, when reception data is received from outside, the reception data and a reception status indicating a status of the reception data in one area of the data writing unit collectively with a single writing operation, in such a manner that the reception status is located at an end of the one area.

Abstract: A first address conversion table stores first address data corresponding to a receiving buffer in a main memory from among address data stored in a page table. A second address conversion table stores second address data corresponding to an area other than the receiving buffer area in the main memory from among the address data stored in the page table. An address-conversion-request determining unit determines whether an address conversion request is for the receiving buffer area. An address converting unit converts the address based on a result of determination by the address-conversion-request determining unit.

Abstract: The DMA data transfer apparatus includes a memory, a communication controller, a DMA controller having a plurality of DMA engines each of which transfers data by DMA to the communication controller from the memory, and a DMA control unit. The DMA control unit determines a division size of transfer data such that the DMA engine can transfer the data, issues a data transfer directive by the DMA to the DMA controller, and controls data transfer by the DMA. The DMA control unit transmits the determination information for determination of the termination of data transfer to the communication controller. The communication controller determines the termination of data transfer based on the determination information transmitted from the DMA control unit.

Abstract: In a data transmitting and receiving apparatus, payloads of packets received from the first device are accumulated in a storage unit, a designated payload volume DSPS is calculated based on DSPS=TP×(1?RR/TR), where TP is a total payload volume of a packet received at a certain time point from the first device, RR is receiving rate of packets, and TR is transmitting rate of packets, and transmission is-started of the payload accumulated in the storage unit to the second device when a payload volume RPS accumulated in the storage unit has reached the designated payload volume DSPS.

Abstract: An event notifying method notifies one or a plurality of events from a device to a processor by queuing to a queue in a processor system having one or a plurality of processors. A number of non-notified events existing in the queue is managed by a counter unit, and an inconsistent state of the counter unit caused by differences in updating timings of the counter unit from the device and the processor is temporarily permitted.

Abstract: A storage device for storing data, while compressing same value of input data, includes an input processing unit, a data storage, a first-in-first-out memory, and an output processing unit. The input processing unit is configured to, upon receiving an input value, determine whether a data value stored in the data storage at an address location corresponding to the input value is valid. If the data value is invalid, the input processing unit stores an initial value at the address location and stores the input value in the first-in-first-out memory. If the data value is valid, the input processing unit performs an arithmetic operation on the data value and stores the operation result in the address location corresponding to the input value.

Abstract: A parallel computer system capable of arbitrarily selecting nodes participating in barrier synchronization while enabling an arbitrary number of node groups to independently execute a process requiring the barrier synchronization. A communication network for the parallel computer system includes a plurality of routing controllers. Each routing controller has a register for setting a predetermined number of receipts of barrier synchronization request messages from other routing controllers, a destination to which the barrier synchronization request message is transmitted, and a destination to which a barrier synchronization establishment message is transmitted.

Abstract: Fiber articles are uniformly dyed with use of a dyeing auxiliary composition which comprises an anionic surfactant of the alpha-hydroxysulfonic acid type and an organic polybasic polymer and has a pH of 9 or higher.