Patents by Inventor Masaaki Nido

Masaaki Nido has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7684133
    Abstract: A thermal contraction stress and a residual contraction stress caused by a difference between the linear expansion coefficients of an optical element unit and a carrier are reduced as much as possible. An optical module includes an optical element unit including optical elements requiring a stress control, and a carrier which supports the optical element unit. As the carrier is made of a material having the same property as that of the substrate material of the optical element, the thermal contraction stress is reduced.
    Type: Grant
    Filed: January 29, 2008
    Date of Patent: March 23, 2010
    Assignee: NEC Corporation
    Inventors: Isao Tomita, Masaaki Nido, Taro Kaneko
  • Patent number: 7585117
    Abstract: Distortion of the temperature control element and the package by thermal deformation or mechanical deformation is prevented from being transmitted to the optical element as stress, and at the same time, constant temperature control of the optical element is realized. An optical element unit including an optical element that requires temperature control and an optical component that does not require temperature control, and a temperature control element for performing temperature adjustment of the optical element are arranged. The temperature control element performs temperature adjustment control of the optical element through a region mounted with the optical component of the optical element unit.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: September 8, 2009
    Inventors: Taro Kaneko, Masaaki Nido, Isao Tomita
  • Publication number: 20080192373
    Abstract: A thermal contraction stress and a residual contraction stress caused by a difference between the linear expansion coefficients of an optical element unit and a carrier are reduced as much as possible. An optical module includes an optical element unit including optical elements requiring a stress control, and a carrier which supports the optical element unit. As the carrier is made of a material having the same property as that of the substrate material of the optical element, the thermal contraction stress is reduced.
    Type: Application
    Filed: January 29, 2008
    Publication date: August 14, 2008
    Inventors: Isao Tomita, Masaaki Nido, Taro Kaneko
  • Publication number: 20080187268
    Abstract: Distortion of the temperature control element and the package by thermal deformation or mechanical deformation is prevented from being transmitted to the optical element as stress, and at the same time, constant temperature control of the optical element is realized. An optical element unit including an optical element that requires temperature control and an optical component that does not require temperature control, and a temperature control element for performing temperature adjustment of the optical element are arranged. The temperature control element performs temperature adjustment control of the optical element through a region mounted with the optical component of the optical element unit.
    Type: Application
    Filed: January 18, 2008
    Publication date: August 7, 2008
    Inventors: TARO KANEKO, Masaaki Nido, Isao Tomita
  • Patent number: 7282745
    Abstract: The present invention provides a semiconductor device having a semiconductor multi-layer structure which includes at least an active layer having at least a quantum well, and the active layer further including at least a luminescent layer of InxAlyGa1-x-yN (0<x<1, 0?y?0.2), wherein a threshold mode gain of each of the at least quantum well is not more than 12 cm?1, and wherein a standard deviation of a microscopic fluctuation in a band gap energy of the at least luminescent layer is in the range of 75 meV to 200 meV.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: October 16, 2007
    Assignee: NEC Corporation
    Inventors: Atsushi Yamaguchi, Masaru Kuramoto, Masaaki Nido
  • Publication number: 20060011903
    Abstract: The present invention provides a semiconductor device having a semiconductor multi-layer structure which includes at least an active layer having at least a quantum well, and the active layer further including at least a luminescent layer of InxAlyGa1-x-yN (0<x<1, 0?y?0.2), wherein a threshold mode gain of each of the at least quantum well is not more than 12 cm?1, and wherein a standard deviation of a microscopic fluctuation in a band gap energy of the at least luminescent layer is in the range of 75 meV to 200 meV.
    Type: Application
    Filed: September 22, 2005
    Publication date: January 19, 2006
    Applicant: NEC CORPORATION
    Inventors: Atsushi Yamaguchi, Masaru Kuramoto, Masaaki Nido
  • Patent number: 6977952
    Abstract: The present invention provides a semiconductor device having a semiconductor multi-layer structure which includes at least an active layer having at least a quantum well, and the active layer further including at least a luminescent layer of InxAlyGa1?x?yN (0<x<1, 0?y?0.2), wherein a threshold mode gain of each of the at least quantum well is not more than 12 cm?1, and wherein a standard deviation of a microscopic fluctuation in a band gap energy of the at least luminescent layer is in the range of 75 meV to 200 meV.
    Type: Grant
    Filed: September 4, 2001
    Date of Patent: December 20, 2005
    Assignee: NEC Corporation
    Inventors: Atsushi Yamaguchi, Masaru Kuramoto, Masaaki Nido
  • Publication number: 20050098793
    Abstract: A nitride based semiconductor photo-luminescent device has an active layer having a quantum well structure. The active layer has both a high dislocation density region and a low dislocation density region that is lower in dislocation density than the high dislocation density region, wherein the low dislocation density region includes a current injection region into which a current is injected, and the active layer is less than 1×1018 cm?3 in impurity concentration.
    Type: Application
    Filed: December 9, 2004
    Publication date: May 12, 2005
    Applicant: NEC CORPORATION
    Inventors: Atsushi Yamaguchi, Masaru Kuramoto, Masaaki Nido
  • Patent number: 6855959
    Abstract: A nitride based semiconductor photo-luminescent device has an active layer having a quantum well structure. The active layer has both a high dislocation density region and a low dislocation density region that is lower in dislocation density than the high dislocation density region, wherein the low dislocation density region includes a current injection region into which a current is injected, and the active layer is less than 1×1018 cm?3 in impurity concentration.
    Type: Grant
    Filed: March 26, 2001
    Date of Patent: February 15, 2005
    Assignee: NEC Corporation
    Inventors: Atsushi Yamaguchi, Masaru Kuramoto, Masaaki Nido
  • Patent number: 6635905
    Abstract: A light-emitting semiconductor device includes an active layer interposed between first-side and second-side cladding layer, and at least one of first-side and second-side optical guide layers. The following four equations are satisfied: 0.15≦h; |x−y|≦0.02; 0.02≦x≦0.06; and 0.34x−0.49≦d1+2h, where “h” is a total thickness of the first-side and second-side optical guide layers; “d1” is a thickness of the first-side cladding layer; “x” is a first Al-index of a first AlGaN bulk crystal which has a first refractive index equal to a first averaged refractive index of the first-side cladding layer; and “y” represents a second Al-index of a second AlGaN bulk crystal which has a second refractive index equal to a second averaged refractive index of the second-side cladding layer.
    Type: Grant
    Filed: September 9, 2002
    Date of Patent: October 21, 2003
    Assignee: NEC Corporation
    Inventors: Masaaki Nido, Masaru Kuramoto, Atsushi Yamaguchi
  • Publication number: 20030052316
    Abstract: A light-emitting semiconductor device includes an active layer interposed between first-side and second-side cladding layer, and at least one of first-side and second-side optical guide layers.
    Type: Application
    Filed: September 9, 2002
    Publication date: March 20, 2003
    Applicant: NEC CORPORATION
    Inventors: Masaaki Nido, Masaru Kuramoto, Atsushi Yamaguchi
  • Patent number: 6423562
    Abstract: For forming a contact electrode to an n-type contact layer of a gallium nitride-based compound semiconductor, the n-type contact layer of the gallium nitride-based compound semiconductor is exposed to an oxygen plasma to form an oxygen-doped surface layer in a surface of the n-type contact layer, and then, an electrode metal is formed on the oxygen-doped surface layer. With this arrangement, an n-type contact electrode having a low specific contact resistance is obtained with good reproducibility, with performing no annealing after formation of the electrode metal.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: July 23, 2002
    Assignee: NEC Corporation
    Inventors: Masaaki Nido, Yukihiro Hisanaga
  • Patent number: 6420198
    Abstract: A semiconductor device and method of forming a current block layer structure includes the steps of providing dielectric stripe masks defining at least a stripe-shaped opening on a surface of a compound semiconductor region having a hexagonal crystal structure, and selectively growing at least a current block layer of a compound semiconductor having the hexagonal crystal structure on the surface of the compound semiconductor region by use of the dielectric stripe masks.
    Type: Grant
    Filed: November 24, 2000
    Date of Patent: July 16, 2002
    Assignee: NEC Corporation
    Inventors: Akitaka Kimura, Masaaki Nido
  • Publication number: 20020030200
    Abstract: The present invention provides a semiconductor device having a semiconductor multi-layer structure which includes at least an active layer having at least a quantum well, and the active layer further including at least a luminescent layer of InxAlyGa1-x-yN (0<x<1, 0≦y≦0.2), wherein a threshold mode gain of each of the at least quantum well is not more than 12 cm−1, and wherein a standard deviation of a microscopic fluctuation in a band gap energy of the at least luminescent layer is in the range of 75 meV to 200 meV.
    Type: Application
    Filed: September 4, 2001
    Publication date: March 14, 2002
    Applicant: NEC Corporation
    Inventors: Atsushi Yamaguchi, Masaru Kuramoto, Masaaki Nido
  • Publication number: 20020020856
    Abstract: For forming a contact electrode to an n-type contact layer of a gallium nitride-based compound semiconductor, the n-type contact layer of the gallium nitride-based compound semiconductor is exposed to an oxygen plasma to form an oxygen-doped surface layer in a surface of the n-type contact layer, and then, an electrode metal is formed on the oxygen-doped surface layer. With this arrangement, an n-type contact electrode having a low specific contact resistance is obtained with good reproducibility, with performing no annealing after formation of the electrode metal.
    Type: Application
    Filed: October 23, 2001
    Publication date: February 21, 2002
    Applicant: NEC CORPORATION
    Inventors: Masaaki Nido, Yukihiro Hisanaga
  • Publication number: 20010054763
    Abstract: For forming a contact electrode to an n-type layer of a gallium nitride-based compound semiconductor, the n-type contact layer of the gallium nitride-based compound semiconductor is exposed to an oxygen plasma to form an oxygen-doped surface layer in a surface of the n-type contact layer, and then, an electrode metal is formed on the oxygen-doped surface layer. With this arrangement, an n-type contact electrode having a low specific contact resistance is obtained with good reproducibility, with performing no annealing after formation of the electrode metal.
    Type: Application
    Filed: January 14, 1998
    Publication date: December 27, 2001
    Inventors: MASAAKI NIDO, YUKIHIRO HISANAGA
  • Patent number: 6329716
    Abstract: For forming a contact electrode to an n-type contact layer of a gallium nitride-based compound semiconductor, the n-type contact layer of the gallium nitride-based compound semiconductor is exposed to an oxygen plasma to form an oxygen-doped surface layer in a surface of the n-type contact layer, and then, an electrode metal is formed on the oxygen-doped surface layer. With this arrangement, an n-type contact electrode having a low specific contact resistance is obtained with good reproducibility, with performing no annealing after formation of the electrode metal.
    Type: Grant
    Filed: January 14, 1998
    Date of Patent: December 11, 2001
    Assignee: NEC Corporation
    Inventors: Masaaki Nido, Yukihiro Hisanaga
  • Publication number: 20010032975
    Abstract: The first present invention provides a nitride based semiconductor photo-luminescent device having an active layer having a quantum well structure, the active layer having both at least a high dislocation density region and at least a low dislocation density region lower in dislocation density than the high dislocation density region, wherein the low dislocation density region includes a current injection region into which a current is injected, and the active layer is less than 1×1018 m−3 in impurity concentration.
    Type: Application
    Filed: March 26, 2001
    Publication date: October 25, 2001
    Applicant: NEC Corporation
    Inventors: Atsushi Yamaguchi, Masaru Kuramoto, Masaaki Nido
  • Patent number: 6201823
    Abstract: A semiconductor device and method of forming a current block layer structure includes the steps of providing dielectric stripe masks defining at least a stripe-shaped opening on a surface of a compound semiconductor region having a hexagonal crystal structure, and selectively growing at least a current block layer of a compound semiconductor having the hexagonal crystal structure on the surface of the compound semiconductor region by use of the dielectric stripe masks.
    Type: Grant
    Filed: December 24, 1997
    Date of Patent: March 13, 2001
    Assignee: NEC Corporation
    Inventors: Akitaka Kimura, Masaaki Nido
  • Patent number: 6096130
    Abstract: A method of crystal growth of a GaN layer with an extremely high surface planarity over a GaAs substrate is provided, wherein a GaAs substrate is heated to a temperature in the range of 600.degree. C. to 700.degree. C. without supplying any group-V element including arsenic to form a Ga-rich surface on the GaAs substrate, before a first source material including N and a second source material including Ga are supplied along with a carrier gas onto a surface of the GaAs substrate to form a GaN layer over the GaAs substrate.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: August 1, 2000
    Assignee: NEC Corporation
    Inventors: Akitaka Kimura, Haruo Sunakawa, Masaaki Nido