Abstract: A memory system includes a non-volatile memory chip and a controller. The non-volatile memory chip is capable of determining an erase voltage according to a temperature of the non-volatile memory chip and a correction parameter. The controller is configured to update the correction parameter of the non-volatile memory chip according to temperature information related to the temperature of the non-volatile memory chip. The non-volatile memory chip determines the erase voltage according to the temperature of the non-volatile memory chip and the updated correction parameter received from the controller.

Abstract: According to one embodiment, a memory system includes a first memory and a memory controller. The first memory is nonvolatile and includes a plurality of memory cell transistors, each of which stores data corresponding to a threshold voltage. The memory controller causes the first memory to execute a read operation to acquire data corresponding to the threshold voltage from the plurality of memory cell transistors on the basis of a result of comparison between the threshold voltage and a read voltage. The memory controller selects a first candidate value from among a plurality of candidate values for the read voltage in accordance with a degree of stress that affects the threshold voltage; and causes the first memory to execute the read operation using the first candidate value as the read voltage.

Abstract: A memory system includes a non-volatile memory chip and a controller. The non-volatile memory chip is capable of determining an erase voltage according to a temperature of the non-volatile memory chip and a correction parameter. The controller is configured to update the correction parameter of the non-volatile memory chip according to temperature information related to the temperature of the non-volatile memory chip. The non-volatile memory chip determines the erase voltage according to the temperature of the non-volatile memory chip and the updated correction parameter received from the controller.

Abstract: According to one embodiment, a memory system includes a first memory and a memory controller. The first memory is nonvolatile and includes a plurality of memory cell transistors, each of which stores data corresponding to a threshold voltage. The memory controller causes the first memory to execute a read operation to acquire data corresponding to the threshold voltage from the plurality of memory cell transistors on the basis of a result of comparison between the threshold voltage and a read voltage. The memory controller selects a first candidate value from among a plurality of candidate values for the read voltage in accordance with a degree of stress that affects the threshold voltage; and causes the first memory to execute the read operation using the first candidate value as the read voltage.

Abstract: A memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes memory cells at intersection locations of stacked word lines and a memory pillar passing through the word lines in a stacking direction, the word lines including a first group of word lines stacked above a second group of word lines. The controller reads data of a first memory cell in a first read mode and reads data of a second memory cell in a second read mode. The first memory cell is, and the second memory cell is not, at an intersection location of a word line that is in a boundary area of the first and second groups of word lines and the memory pillar. The boundary area is adjacent to a location of the memory pillar where a width of the memory pillar discontinuously changes along the stacking direction.

Abstract: A memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes memory cells at intersection locations of stacked word lines and a memory pillar passing through the word lines in a stacking direction, the word lines including a first group of word lines stacked above a second group of word lines. The controller reads data of a first memory cell in a first read mode and reads data of a second memory cell in a second read mode. The first memory cell is, and the second memory cell is not, at an intersection location of a word line that is in a boundary area of the first and second groups of word lines and the memory pillar. The boundary area is adjacent to a location of the memory pillar where a width of the memory pillar discontinuously changes along the stacking direction.

Abstract: According to one embodiment, a memory system includes a first nonvolatile memory, and a controller. The controller executes, to the first memory, a program operation first and a first read operation next. The program operation is an operation including (i) acquiring a first temperature, (ii) storing the first temperature, and (iii) controlling the access circuit to set a threshold voltage of a memory cell transistor at a value corresponding to first data. The first read operation is an operation for (i) acquiring a second temperature, (ii) computing a difference between the second and the first temperature, (iii) acquiring a first determination voltage, (iv) correcting the first determination voltage according to the difference, and (v) controlling the first memory to acquire second data corresponding to the threshold voltage on the basis of a comparison between the threshold voltage of the memory cell transistor and the corrected first determination voltage.

Abstract: According to one embodiment, a memory system includes a memory device and a controller. The controller is configured to make the memory device apply a first verify voltage to a first word line for determining whether writing of a first data value into a first cell transistor has been completed. The controller is configured to make the memory device apply a second verify voltage to a second word line for determining whether writing of the first data value into a second cell transistor has been completed. The second verify voltage is different from the first verify voltage.

Abstract: A semiconductor memory device includes a nonvolatile memory and a controller. The nonvolatile memory has a plurality of memory cells that are connected to word lines to which a read voltage is applied at the time of reading data stored in the memory cells. The controller is configured to determine a read voltage for a target memory cell by selecting a tracking parameter based on a word line connected to the target memory cell and an elapsed time from a previous access to a group of memory cells including the target memory cell, and executing a tracking process on the memory cells also connected to the word line connected to the target memory cell using the selected tracking parameter.

Abstract: According to one embodiment, a memory system comprises a non-volatile semiconductor memory, a memory and a controller. The memory stores a management table including a plurality of parameters for managing the non-volatile semiconductor memory. The controller is configured to control the operation of the non-volatile semiconductor memory based on a first value of the parameters contained in the management table. The controller obtains a second value corresponding to the parameters from an operation log of the non-volatile semiconductor memory, compares the second value of the parameters with the first value, calculates the difference between the second value of the parameters and the first value when they are different from each other, calculates a correction value for correcting the first value when the difference is greater than a third value, and updates the first value of the management table based on the correction value.

Abstract: According to one embodiment, a memory system includes a memory and controller. The controller repeatedly performs an erase voltage application process for data stored in a target area in the memory. The controller performs an erase verification process for determining whether the erase is successful using erase verification voltage. The controller determines whether an erase time is longer than a first threshold value. The controller sets the target area to a use prohibition state when the erase time is longer than the first threshold value.

Abstract: According to one embodiment, a memory system includes a first nonvolatile memory, and a controller. The controller executes, to the first memory, a program operation first and a first read operation next. The program operation is an operation including (i) acquiring a first temperature, (ii) storing the first temperature, and (iii) controlling the access circuit to set a threshold voltage of a memory cell transistor at a value corresponding to first data. The first read operation is an operation for (i) acquiring a second temperature, (ii) computing a difference between the second and the first temperature, (iii) acquiring a first determination voltage, (iv) correcting the first determination voltage according to the difference, and (v) controlling the first memory to acquire second data corresponding to the threshold voltage on the basis of a comparison between the threshold voltage of the memory cell transistor and the corrected first determination voltage.

Abstract: A memory system includes a semiconductor memory chip including a substrate, an array of memory cells in arranged each of a plurality of levels in a thickness direction of the substrate, and a plurality of word lines arranged in the thickness direction, each of the word lines being connected to memory cells in one of the levels, and a controller. The controller is configured to determine an offset value with respect to each of a plurality of word line groups that are organized from the plurality of word lines along the thickness direction, and, with respect to each of the word line groups, set a voltage to be applied to the word line group during at least one of write, read, and erase operations, based on a base parameter value and the offset value corresponding to the word line group.

Abstract: Aspects of the present disclosure include a memory system monitors at least one of an erasing time length and a programming time length of each of physical blocks included in a first logical block among a plurality of logical blocks. The memory system disassembles the first logical block among the plurality of logical blocks when both of a first physical block and a second physical block exist in the first logical block, the first physical block having an erasing time length or a programming time length falling within a first range, and the second physical block having an erasing time length or a programming time length falling outside the first range.

Abstract: According to one embodiment, a control system includes: a memory device; and a controller. The memory device includes a first cell transistor. The controller is configured to store information on a first temperature associated with a temperature of the memory device upon a write of data in the first cell transistor, obtain a second temperature of the memory device, determine an adjustment from adjustments based on a combination of the first temperature and the second temperature, and instruct the memory device to use for a first parameter a first value and a value which is based on the determined adjustment to read data from the first cell transistor.

Abstract: According to one embodiment, a memory device includes a controller, and a nonvolatile memory in which an erase operation is controlled by the controller, the nonvolatile memory including blocks, the erase operation executing every block, the nonvolatile memory transferring a first reply showing a completion of the erase operation and a fail bit count showing a number of memory cells in which a data erase is uncompleted after the completion of the erase operation to the controller. The controller selects a target block as a target of the erase operation based on the fail bit count.

Abstract: According to one embodiment, a memory system includes a memory and controller. The controller repeatedly performs an erase voltage application process for data stored in a target area in the memory. The controller performs an erase verification process for determining whether the erase is successful using erase verification voltage. The controller determines whether an erase time is longer than a first threshold value. The controller sets the target area to a use prohibition state when the erase time is longer than the first threshold value.

Abstract: According to one embodiment, a control system includes: a memory device; and a controller. The memory device includes a first cell transistor. The controller is configured to store information on a first temperature associated with a temperature of the memory device upon a write of data in the first cell transistor, obtain a second temperature of the memory device, determine an adjustment from adjustments based on a combination of the first temperature and the second temperature, and instruct the memory device to use for a first parameter a first value and a value which is based on the determined adjustment to read data from the first cell transistor.

Abstract: According to one embodiment, a memory system includes a memory device and a controller. The controller is configured to make the memory device apply a first verify voltage to a first word line for determining whether writing of a first data value into a first cell transistor has been completed. The controller is configured to make the memory device apply a second verify voltage to a second word line for determining whether writing of the first data value into a second cell transistor has been completed. The second verify voltage is different from the first verify voltage.

Abstract: A semiconductor memory device includes a nonvolatile memory and a controller. The nonvolatile memory has a plurality of memory cells that are connected to word lines to which a read voltage is applied at the time of reading data stored in the memory cells. The controller is configured to determine a read voltage for a target memory cell by selecting a tracking parameter based on a word line connected to the target memory cell and an elapsed time from a previous access to a group of memory cells including the target memory cell, and executing a tracking process on the memory cells also connected to the word line connected to the target memory cell using the selected tracking parameter.