Abstract: A static verification program according to the present invention reads a circuit description and property. In a static verification step, static verification of the circuit description is performed on the basis of the property and the number of states that can be reached and the number of states that is reached are calculated. In a search coverage value calculation step, a search coverage value is calculated on the basis of the number of states that can be reached and the number of states that is reached. In a display step, the search coverage value is displayed in a state in which the search coverage value can be visually checked.

Abstract: A static verification program according to the present invention reads a circuit description and property. In a static verification step, static verification of the circuit description is performed on the basis of the property and the number of states that can be reached and the number of states that is reached are calculated. In a search coverage value calculation step, a search coverage value is calculated on the basis of the number of states that can be reached and the number of states that is reached. In a display step, the search coverage value is displayed in a state in which the search coverage value can be visually checked.

Abstract: A semiconductor integrated circuit includes a target circuit configured to operate in a normal mode, to form a scan chain to serially transfer a test data through the scan chain, in a scan path test mode, and to form a plurality of sub scan chains to save an internal node data in a memory in a save mode; and a backup control circuit configured to supply to the target circuit, a system clock signal in the normal mode, a test clock signal in the scan path test mode, and a save/recover clock signal in the save mode, and to control the target circuit and the memory such operations in the normal mode, the scan path test mode, and the save mode are performed. The test clock signal is slower than the system clock signal, and the save/recover clock signal is slower than the system clock signal and faster than the test clock signal.

Abstract: A semiconductor integrated circuit includes a target circuit with at least a scan chain having sub scan chains of stages to sequentially shift a test data in response to a clock signal in a scan path test mode, and each of the sub scan chains includes first flip-flops connected in series. A backup control circuit controls the target circuit and a memory such that a plurality of sub internal state data of a data indicating an internal state of the target circuit are stored as a plurality of write data in the memory in a save mode through the sub scan chains and the plurality of sub internal state data are read out from the memory as a plurality of read data and set in the sub scan chains in a restore mode.

Abstract: A semiconductor integrated circuit includes a target circuit configured to operate in a normal mode, to form a scan chain to serially transfer a test data through the scan chain, in a scan path test mode, and to form a plurality of sub scan chains to save an internal node data in a memory in a save mode; and a backup control circuit configured to supply to the target circuit, a system clock signal in the normal mode, a test clock signal in the scan path test mode, and a save/recover clock signal in the save mode, and to control the target circuit and the memory such operations in the normal mode, the scan path test mode, and the save mode are performed. The test clock signal is slower than the system clock signal, and the save/recover clock signal is slower than the system clock signal and faster than the test clock signal.

Abstract: Provided is an adder composed of (N+1) circuit stages in the ease of 2.sup.N bits. In the case of N=4 (that is, 16 bits), provisional carries that indicate the case where carry is produced from a low order bit and the case where no carry is produced therefrom are generated by conditional cells in a first circuit stage. In second to fourth circuit stages, the provisional carries corresponding to higher seven bits other than the most significant bit are converted into provisional sums by converters in a circuit stage in which the provisional carries are transferred. In addition, actual carry signals are selected from the provisional carries corresponding to lower seven bits other than the least significant bit in a circuit stage in which the provisional carries are transferred. In a fifth circuit stage, bit sums for each of the bits are generated and outputted.

Abstract: A semiconductor integrated circuit includes a target circuit with at least a scan chain having sub scan chains of stages to sequentially shift a test data in response to a clock signal in a scan path test mode, and each of the sub scan chains includes first flip-flops connected in series. A backup control circuit controls the target circuit and a memory such that a plurality of sub internal state data of a data indicating an internal state of the target circuit are stored as a plurality of write data in the memory in a save mode through the sub scan chains and the plurality of sub internal state data are read out from the memory as a plurality of read data and set in the sub scan chains in a restore mode.

Abstract: Provided is an adder composed of (N+1) circuit stages in the case of 2N bits. In the case of N=4 (that is, 16 bits), provisional carriers that indicate the case where carry is produced from a low order bit and the case where no carry is produced therefrom are generated by conditional cells in a first circuit stage. In second to fourth circuit stages, the provisional carriers corresponding to higher seven bits other than the most significant bit are converted into provisional sums by converters in a circuit stage in which the provisional carriers are transferred. In addition, actual carry signals are selected from the provisional carriers corresponding to lower seven bits other than the least significant bit in a circuit stage in which the provisional carriers are transferred. In a fifth circuit stage, bit sums for each of the bits are generated and outputted.