Patents by Inventor Masaaki Tanio

Masaaki Tanio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240146587
    Abstract: A wireless access system includes: a centralized control station; and an access point. The access point performs a pulse width modulation process on an analog uplink signal, thereby to generate an analog modulation signal; and converts the analog modulation signal to an optical uplink signal. The centralized control station converts the optical uplink signal to an electrical uplink signal; performs, on the electrical uplink signal, a filtering process for extracting an analog extraction signal including a signal component corresponding to the analog uplink signal; and converts the analog extraction signal to a digital uplink signal representing a signal level of the analog extraction signal by two or more bits.
    Type: Application
    Filed: October 12, 2023
    Publication date: May 2, 2024
    Applicant: NEC Corporation
    Inventor: Masaaki TANIO
  • Patent number: 11831347
    Abstract: A parameter determination apparatus (2) includes: a first learning device (2111) learning a weight between a [j?1]-th layer (j is an integer that satisfies a condition that “2?j?the number of the layer”) and a [j]-th layer to which an output of the [j?1]-th layer is inputted among a plurality of layers of a neural network; a selecting device (2112) selecting at least one valid path for each node included in the [j]-th layer from a plurality of connection paths that connect nodes in the [j?1]-th layer and nodes in the [j]-th layer, respectively, on the basis of the weight learned by the first learning device; and a second learning device (2113) learning at least one of the weight and a bias as the parameters relating to a network structure between the [j?1]-th layer and the [j]-th layer on the basis of the sample signal, the label signal and the valid path.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: November 28, 2023
    Assignee: NEC CORPORATION
    Inventors: Masaaki Tanio, Norifumi Kamiya, Naoto Ishii
  • Publication number: 20230378984
    Abstract: A parameter changing device according to the present disclosure includes: a multiplier multiplying a test signal by a back-off rate; a first distortion compensation simulation unit performing distortion compensation processing on a signal acquired by the multiplication, by using a stored parameter; a scaling unit scaling an output signal of the first distortion compensation simulation unit; a second distortion compensation simulation unit performing distortion compensation processing on the test signal, by using a parameter different from the first distortion compensation simulation unit; a differential unit calculating an error between a value of a signal acquired by the scaling and a value of an output signal of the second distortion compensation simulation unit; an approximation error minimization unit calculating a parameter of the second distortion compensation simulation unit minimizing the error; and an output unit outputting a parameter of the second distortion compensation simulation unit to a distor
    Type: Application
    Filed: May 15, 2023
    Publication date: November 23, 2023
    Applicant: NEC Corporation
    Inventor: Masaaki TANIO
  • Publication number: 20230275788
    Abstract: A signal transmission apparatus (1) includes: a distortion compensation unit (11) for performing a distortion compensation processing on an input signal (x) by using a Neural Network (112) including L+1 arithmetic layers that include L (L is a variable number representing an integer equal to or larger than 1) hidden layer (112M) and an output layer (112O); a storage unit (13) for storing parameter sets (131) each of which includes a parameter for Q (Q is a variable number representing an integer equal to or smaller than L) arithmetic layer of the L+1 arithmetic layers; and an application unit (142) for selecting one parameter set from the parameter sets based on a signal pattern of the input signal and applying the parameter included in the selected one parameter set to the M number of arithmetic layer, a parameter of another arithmetic layer of the L+1 arithmetic layers, which is other than the Q arithmetic layer, is fixed.
    Type: Application
    Filed: June 10, 2020
    Publication date: August 31, 2023
    Applicant: NEC Corporation
    Inventor: Masaaki TANIO
  • Publication number: 20230054311
    Abstract: A delta-sigma modulation apparatus performs delta-sigma modulation on a first signal as an input signal and outputs a second signal, outputs, using the second signal and a third signal generated through a transmission process of the second signal, a fourth signal that is an approximated value of a signal which is generated through at least part of the transmission process, and performs the delta-sigma modulation on the first signal using the fourth signal and outputs the second signal.
    Type: Application
    Filed: August 4, 2022
    Publication date: February 23, 2023
    Applicant: NEC Corporation
    Inventors: Masaaki TANIO, Naoto ISHII, Kazushi MURAOKA
  • Patent number: 11515846
    Abstract: An in-band extraction unit is configured to extract an in-band from an output signal. An out-band extraction unit is configured to extract at least one pair of out-bands including a low frequency side out-band and a high frequency side out-band from the output signal. An ADC is configured to convert the extracted in-band and out-bands to digital signals. A signal processing unit is configured to process information included in the digital signals converted by the analog to digital converter and adjust an operation of predistorting an input baseband digital signal to generate the output signal.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: November 29, 2022
    Assignee: NEC CORPORATION
    Inventors: Soubhik Deb, Masaaki Tanio
  • Publication number: 20220360231
    Abstract: An input signal is input to a main power amplifier and an auxiliary power amplifier. A combiner is connected to an output of the main power amplifier and an output of the auxiliary power amplifier. The combiner includes an impedance converter, first and second lumped elements. The impedance converter is connected to a combining point. The first lumped element is connected between the output of the main power amplifier and the combining point. The second lumped element is connected between the output of the auxiliary power amplifier and the combining point. A line length between the output of the main power amplifier and the combining point is the same as that between a line length between the output of the auxiliary power amplifier and the combining point.
    Type: Application
    Filed: February 12, 2020
    Publication date: November 10, 2022
    Applicant: NEC Corporation
    Inventor: Masaaki TANIO
  • Publication number: 20220345163
    Abstract: A parameter determination apparatus (2) includes: a first learning device (2111) learning a weight between a [j?1]-th layer (j is an integer that satisfies a condition that “2?j?the number of the layer”) and a [j]-th layer to which an output of the [j?1]-th layer is inputted among a plurality of layers of a neural network; a selecting device (2112) selecting at least one valid path for each node included in the [j]-th layer from a plurality of connection paths that connect nodes in the [j?1]-th layer and nodes in the [j]-th layer, respectively, on the basis of the weight learned by the first learning device; and a second learning device (2113) learning at least one of the weight and a bias as the parameters relating to a network structure between the [j?1]-th layer and the [j]-th layer on the basis of the sample signal, the label signal and the valid path.
    Type: Application
    Filed: September 2, 2020
    Publication date: October 27, 2022
    Applicant: NEC Corporation
    Inventors: Masaaki TANIO, Norifumi KAMIYA, Naoto ISHII
  • Patent number: 11290165
    Abstract: This transmitter is provided with: a digital delay circuit which delays a 1-bit digital RF signal on the basis of another 1-bit digital RF signal; an amplifier which amplifies a signal output by the digital delay circuit; and a band-pass filter which allows signals in a prescribed frequency band, from among signals output by the amplifier, to pass. A signal output by the band-pass filter is input into a corresponding one antenna element from among a plurality of antenna elements, and controls the directionality of a beam formed by the plurality of antenna elements.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: March 29, 2022
    Assignee: NEC CORPORATION
    Inventors: Masaaki Tanio, Shinichi Hori, Tomoyuki Yamase
  • Publication number: 20220085837
    Abstract: A parameter determination apparatus adds a third layer between first and second layers of the neural network. The third layer includes a third node not including a non-linear activation function. Outputs of first nodes of the first layer is inputted to the third node The number of the third node of the third layer is smaller than the number of second nodes of the second layer. The parameter determination apparatus further learns a weight between the third and second layers as a part of the parameters and selects, as a part of the parameters, one valid path used as a valid connecting path in the neural network for each second node from connecting paths that connect the third node and the second nodes on the basis of the learned weight.
    Type: Application
    Filed: September 3, 2021
    Publication date: March 17, 2022
    Applicant: NEC Corporation
    Inventor: Masaaki Tanio
  • Patent number: 11190204
    Abstract: A second-order ?? modulator includes: a two-stage integrator; a first arithmetic operation circuit; and a second arithmetic operation circuit. The two-stage integrator includes a plurality of adder arrays, each of which includes a plurality of adders. The plurality of adder arrays includes first to fourth adder arrays. An output of a last stage of the second adder array is fed back as an input of a first stage of the first adder array. An output of a last stage of the fourth adder array is fed back as an input of a first stage of the third adder array. A sum bit string obtained in the first adder array is input to the third adder array. A sum bit string obtained in the second adder array is input to the fourth adder array.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: November 30, 2021
    Assignee: NEC CORPORATION
    Inventor: Masaaki Tanio
  • Publication number: 20210297125
    Abstract: This transmitter is provided with: a digital delay circuit which delays a 1-bit digital RF signal on the basis of another 1-bit digital RF signal; an amplifier which amplifies a signal output by the digital delay circuit; and a band-pass filter which allows signals in a prescribed frequency band, from among signals output by the amplifier, to pass. A signal output by the band-pass filter is input into a corresponding one antenna element from among a plurality of antenna elements, and controls the directionality of a beam formed by the plurality of antenna elements.
    Type: Application
    Filed: September 20, 2017
    Publication date: September 23, 2021
    Applicant: NEC Corporation
    Inventors: Masaaki TANIO, Shinichi HORI, Tomoyuki YAMASE
  • Publication number: 20210218413
    Abstract: A second-order ?? modulator includes: a two-stage integrator; a first arithmetic operation circuit; and a second arithmetic operation circuit. The two-stage integrator includes a plurality of adder arrays, each of which includes a plurality of adders. The plurality of adder arrays includes first to fourth adder arrays. An output of a last stage of the second adder array is fed back as an input of a first stage of the first adder array. An output of a last stage of the fourth adder array is fed back as an input of a first stage of the third adder array. A sum bit string obtained in the first adder array is input to the third adder array. A sum bit string obtained in the second adder array is input to the fourth adder array.
    Type: Application
    Filed: December 4, 2018
    Publication date: July 15, 2021
    Applicant: NEC Corporation
    Inventor: Masaaki TANIO
  • Publication number: 20210184635
    Abstract: An in-band extraction unit is configured to extract an in-band from an output signal. An out-band extraction unit is configured to extract at least one pair of out-bands including a low frequency side out-band and a high frequency side out-band from the output signal. An ADC is configured to convert the extracted in-band and out-bands to digital signals. A signal processing unit is configured to process information included in the digital signals converted by the analog to digital converter and adjust an operation of predistorting an input baseband digital signal to generate the output signal.
    Type: Application
    Filed: December 4, 2017
    Publication date: June 17, 2021
    Applicant: NEC Corporation
    Inventors: Soubhik DEB, Masaaki TANIO
  • Patent number: 10778264
    Abstract: A transmitter includes a plurality of transmitter circuits configured to generate signals that are within the same frequency band; and a feedback circuit that is shared by the plurality of transmitter circuits, the feedback circuit being configured to feed back a part of a transmission amplification signal to a transmitter circuit, the transmission amplification signal being output from each of the plurality of transmitter circuits through a transmission amplifier, and the transmitter circuit being configured to output the transmission amplification signal among the plurality of transmitter circuits.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: September 15, 2020
    Assignee: NEC CORPORATION
    Inventors: Wataru Hattori, Masaaki Tanio
  • Patent number: 10749480
    Abstract: A transmitter includes: a transmission circuit that outputs, via a transmission amplifier, transmission signals of a same frequency band; and a feedback circuit that feeds back, to the transmission circuit, a distortion compensation coefficient that is used to compensate for distortion of the transmission signals. The feedback circuit includes: a delay circuit that delays each of the transmission signals by a different amount of time; a combining unit that combines the delayed transmission signals to generate a combined signal; a signal conversion unit that converts a frequency of the combined signal to a different frequency using a local signal that is common among the transmission signals, and generates a demodulated digital signal from the combined signal of which the frequency has been converted; and a distortion compensation calculation unit that calculates the distortion compensation coefficient based on the demodulated digital signal.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: August 18, 2020
    Assignee: NEC CORPORATION
    Inventors: Masaaki Tanio, Wataru Hattori
  • Patent number: 10707893
    Abstract: A second-order ?? modulator includes a plurality of integrators and a parallel higher-bit processing part, and the parallel higher-bit processing part includes a plurality of addition and determination processing sections. The addition and determination processing section receives first and second carry inputs and first and second state inputs, and outputs a quantized output and first and second state outputs. A first selector selects one set from sets of the first and the second state outputs from the plurality of addition and determination processing sections and outputs the selected set, and a second selector selects one quantized output from the quantized outputs from the plurality of addition and determination processing sections. An output of the first selector is used as a selection control signal for the first and the second selectors.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: July 7, 2020
    Assignee: NEC CORPORATION
    Inventor: Masaaki Tanio
  • Publication number: 20200076379
    Abstract: A transmitter includes: a transmission circuit that outputs, via a transmission amplifier, transmission signals of a same frequency band; and a feedback circuit that feeds back, to the transmission circuit, a distortion compensation coefficient that is used to compensate for distortion of the transmission signals. The feedback circuit includes: a delay circuit that delays each of the transmission signals by a different amount of time; a combining unit that combines the delayed transmission signals to generate a combined signal; a signal conversion unit that converts a frequency of the combined signal to a different frequency using a local signal that is common among the transmission signals, and generates a demodulated digital signal from the combined signal of which the frequency has been converted; and a distortion compensation calculation unit that calculates the distortion compensation coefficient based on the demodulated digital signal.
    Type: Application
    Filed: April 26, 2018
    Publication date: March 5, 2020
    Applicant: NEC Corporation
    Inventors: Masaaki TANIO, Wataru HATTORI
  • Patent number: 10574199
    Abstract: The purpose of the present invention is to provide an amplifier having high signal-to-noise ratio of a transmitted signal and high electrical efficiency. Another purpose is to suppress complexity of amplifier's wiring connecting a signal generator that generates a binary digital signal and an amplification unit that amplifies the same. This amplifier generates a binary digital signal. The amplifier further generates a K-value digital signal (K is an integer greater than or equal to 3) from the binary digital signal and generating a plurality of binary digital signals from the K-value digital signal. The amplifier amplifies each of the plurality of binary digital signals, and combines the plurality of amplified binary digital signals and generating a combined signal having a substantially proportional relationship with the K-value digital signal.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: February 25, 2020
    Assignee: NEC CORPORATION
    Inventors: Shinichi Hori, Tomoyuki Yamase, Masaaki Tanio
  • Publication number: 20200014412
    Abstract: A transmitter includes a plurality of transmitter circuits configured to generate signals that are within the same frequency band; and a feedback circuit that is shared by the plurality of transmitter circuits, the feedback circuit being configured to feed back a part of a transmission amplification signal to a transmitter circuit, the transmission amplification signal being output from each of the plurality of transmitter circuits through a transmission amplifier, and the transmitter circuit being configured to output the transmission amplification signal among the plurality of transmitter circuits.
    Type: Application
    Filed: February 8, 2017
    Publication date: January 9, 2020
    Applicant: NEC Corporation
    Inventors: Wataru HATTORI, Masaaki TANIO