Patents by Inventor Masaaki Yasumoto

Masaaki Yasumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4849921
    Abstract: An arithmetic circuit has a first subtracter receiving first and second input signals which are composed of a plurality of bits and operative to output a first output signal representative of the first input signal minus the second input signal, and a second subtracter receiving the first and second input signals so as to output a second output signal representative of the second input signal minus the first input signal. A selector receives the first and second output signals and operates in response to one of the first and second output signals so as to alternately output the first and second output signals.
    Type: Grant
    Filed: June 19, 1986
    Date of Patent: July 18, 1989
    Assignee: NEC Corporation
    Inventors: Masaaki Yasumoto, Tadayoshi Enomoto, Masakazu Yamashina
  • Patent number: 4612083
    Abstract: A process of fabricating a three-dimensional semiconductor device, comprising the steps of preparing at least two multilayer structures each including at least one semiconductor element and a conductor connected at one end to the semiconductor element and having at the other end an exposed surface, at least one of the multilayer structures further including a thermally fusible insulating adhesive layer having a surface coplanar with the exposed surface of the conductor, positioning the multilayer structures so that the exposed surfaces of the respective conductors of the multilayer structures are spaced apart from and aligned with each other, moving at least one of the multilayer structures with respect to the other until the exposed surfaces of the conductors of the multilayer structures contact each other, and heating the multilayer structures for causing the insulating adhesive layer of at least one of the multilayer structures to thermally fuse to the other multilayer structure with the semiconductor elem
    Type: Grant
    Filed: July 17, 1985
    Date of Patent: September 16, 1986
    Assignee: NEC Corporation
    Inventors: Masaaki Yasumoto, Hiroshi Hayama, Tadayoshi Enomoto