Patents by Inventor Masafumi Kubota

Masafumi Kubota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240069825
    Abstract: A print system has a terminal device, a printer including a printing unit, and a service server including a memory storing user identification information and a print-permitted amount. The print system has a controller to perform displaying a charge screen for receiving a charge of a printing amount to be printed by the printing unit, acquiring the received printing amount to be charged and first user identification information of a user, adding the acquired printing amount to the print-permitted amount associated with the first user identification information, acquiring a print-completed amount printed by the printing unit of the printer and second user identification information of a user who instructed the printing of the print-completed amount, subtracting the acquired print-completed amount from the print-permitted amount associated with the second user identification information stored in the memory, and determining whether printing is permitted or not based on the print-permitted amount.
    Type: Application
    Filed: October 24, 2023
    Publication date: February 29, 2024
    Inventors: Masafumi Kawaguchi, Hirotaka Kubota
  • Publication number: 20240029565
    Abstract: A warning device includes: a right turn determining part that determines that a vehicle will turn right if a turn signal thereof is in a right turn signal state, and vehicle speed thereof is equal to or less than creep speed; an oncoming vehicle is approach determining part that determines that another vehicle is approaching the vehicle as an oncoming vehicle if the vehicle will turn right, a vector indicating a travel direction of the vehicle and a vector indicating a travel direction of the other vehicle intersect with each other, and a position of the other vehicle is included in a predetermined angle range in front of the vehicle; and an output control part that causes a warning to be output if the other vehicle is approaching the vehicle, and a yaw rate of the vehicle is equal to or greater than a predetermined angular velocity.
    Type: Application
    Filed: August 25, 2021
    Publication date: January 25, 2024
    Inventors: Masahide UNNO, Masafumi KUBOTA
  • Publication number: 20230322250
    Abstract: A warning device includes: an other vehicle approach determining part that determines that another vehicle is approaching a subject vehicle from a side of the subject vehicle A, if a subject vehicle travel vector and an other vehicle travel vector intersect with each other, and if the position of the other vehicle is included in a predetermined angle range defined laterally with respect to an azimuth angle of the subject vehicle A while it is determined that the subject vehicle A during traveling is in a temporary stop state, where its vehicle speed is equal to or less than a predetermined vehicle speed; and an output control part that causes a warning output part to output a warning on condition that the subject vehicle A in the temporary stop state starts travelling while the other vehicle is approaching the subject vehicle A.
    Type: Application
    Filed: August 23, 2021
    Publication date: October 12, 2023
    Inventors: Masahide UNNO, Masafumi KUBOTA
  • Patent number: 8574972
    Abstract: After a fin-semiconductor region (13) is formed on a substrate (11), impurity-containing gas and oxygen-containing gas are used to perform plasma doping on the fin-semiconductor region (13). This forms impurity-doped region (17) in at least side portions of the fin-semiconductor region (13).
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: November 5, 2013
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Sasaki, Masafumi Kubota, Shigenori Hayashi
  • Patent number: 8216922
    Abstract: Plasma doping is performed using a plasma made of a gas containing an impurity which will serve as a dopant. In this case, at least one of plasma generation high-frequency power and biasing high-frequency power is supplied in the form of pulses.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: July 10, 2012
    Assignee: Panasonic Corporation
    Inventors: Shigenori Hayashi, Masafumi Kubota, Yuichiro Sasaki
  • Publication number: 20120034750
    Abstract: After a fin-semiconductor region (13) is formed on a substrate (11), impurity-containing gas and oxygen-containing gas are used to perform plasma doping on the fin-semiconductor region (13). This forms impurity-doped region (17) in at least side portions of the fin-semiconductor region (13).
    Type: Application
    Filed: October 28, 2010
    Publication date: February 9, 2012
    Inventors: Yuichiro Sasaki, Masafumi Kubota, Shigenori Hayashi
  • Publication number: 20110303146
    Abstract: There is provided a regulating gas suction device, which forms a regulating gas flow for use in preventing air outside a vacuum container trying to invade into the vacuum container through a sealing member that tightly closes a gap between an upper end surface of the vacuum container and a peripheral edge of a top pate being opposed to each other from flowing toward a substrate at a coupling portion between the top plate and the vacuum container.
    Type: Application
    Filed: December 2, 2010
    Publication date: December 15, 2011
    Inventors: Osamu Nishijima, Yuichiro Sasaki, Masafumi Kubota, Mototsugu Ogura, Katsumi Okashita
  • Publication number: 20110230038
    Abstract: Plasma doping is performed using a plasma made of a gas containing an impurity which will serve as a dopant. In this case, at least one of plasma generation high-frequency power and biasing high-frequency power is supplied in the form of pulses.
    Type: Application
    Filed: March 18, 2011
    Publication date: September 22, 2011
    Inventors: Shigenori Hayashi, Masafumi Kubota, Yuichiro Sasaki
  • Patent number: 7800181
    Abstract: A gate electrode is formed on a semiconductor substrate containing silicon, then source/drain regions are formed in regions of the semiconductor substrate located to both sides of the gate electrode, and then a nickel alloy silicide layer is formed on at least either the gate electrode or the source/drain regions. In the step of forming the nickel alloy silicide layer, a nickel alloy film and a nickel film are sequentially deposited on the semiconductor substrate and thereafter subjected to heat treatment.
    Type: Grant
    Filed: October 18, 2006
    Date of Patent: September 21, 2010
    Assignee: Panasonic Corporation
    Inventors: Yasutoshi Okuno, Michikazu Matsumoto, Masafumi Kubota, Seiji Ueda, Hiroshi Iwai, Kazuo Tsutsui, Kuniyuki Kakushima
  • Publication number: 20070093047
    Abstract: A gate electrode is formed on a semiconductor substrate containing silicon, then source/drain regions are formed in regions of the semiconductor substrate located to both sides of the gate electrode, and then a nickel alloy silicide layer is formed on at least either the gate electrode or the source/drain regions. In the step of forming the nickel alloy silicide layer, a nickel alloy film and a nickel film are sequentially deposited on the semiconductor substrate and thereafter subjected to heat treatment.
    Type: Application
    Filed: October 18, 2006
    Publication date: April 26, 2007
    Inventors: Yasutoshi Okuno, Michikazu Matsumoto, Masafumi Kubota, Seiji Ueda, Hiroshi Iwai, Kazuo Tsutsui, Kuniyuki Kakushima
  • Patent number: 7144761
    Abstract: A semiconductor device includes metal interconnects made from a multi-layer film composed of a first metal film formed on a semiconductor substrate with an insulating film sandwiched therebetween and a second metal film deposited on the first metal film. An interlayer insulating film having a via hole is formed on the metal interconnects. A third metal film is selectively grown on the second metal film within the via hole, so that a plug can be formed from the third metal film.
    Type: Grant
    Filed: October 6, 2004
    Date of Patent: December 5, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideo Nakagwa, Eiji Tamaoka, Masafumi Kubota, Tetsuya Ueda
  • Publication number: 20060205131
    Abstract: An underlying insulting film of silicon oxide, a gate insulating film of hafnium oxide, a gate electrode of polysilicon, and side walls of silicon oxide are formed above an element formation region of a semiconductor substrate. In the upper portion of the element formation region of the semiconductor substrate, source and drain areas and extension areas are formed by implantations of respective types. Thereafter, the scan speed of the semiconductor substrate and the pulse interval and the peak power of laser beam are adjusted to irradiate only the vicinity of the surface of the semiconductor substrate with laser beam for 0.1 second so that the vicinity of the surface of the semiconductor substrate has a temperature of 1150 to 1250° C. Thus, heat treatments for the gate insulating film and the source and drain areas are performed.
    Type: Application
    Filed: April 27, 2006
    Publication date: September 14, 2006
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Masafumi Kubota, Shigenori Hayashi
  • Patent number: 7094639
    Abstract: An underlying insulting film of silicon oxide, a gate insulating film of hafnium oxide, a gate electrode of polysilicon, and side walls of silicon oxide are formed above an element formation region of a semiconductor substrate. In the upper portion of the element formation region of the semiconductor substrate, source and drain areas and extension areas are formed by implantations of respective types. Thereafter, the scan speed of the semiconductor substrate and the pulse interval and the peak power of laser beam are adjusted to irradiate only the vicinity of the surface of the semiconductor substrate with laser beam for 0.1 second so that the vicinity of the surface of the semiconductor substrate has a temperature of 1150 to 1250° C. Thus, heat treatments for the gate insulating film and the source and drain areas are performed.
    Type: Grant
    Filed: September 16, 2003
    Date of Patent: August 22, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masafumi Kubota, Shigenori Hayashi
  • Publication number: 20050059231
    Abstract: A semiconductor device includes metal interconnects made from a multi-layer film composed of a first metal film formed on a semiconductor substrate with an insulating film sandwiched therebetween and a second metal film deposited on the first metal film. An interlayer insulating film having a via hole is formed on the metal interconnects. A third metal film is selectively grown on the second metal film within the via hole, so that a plug can be formed from the third metal film.
    Type: Application
    Filed: October 6, 2004
    Publication date: March 17, 2005
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideo Nakagawa, Eiji Tamaoka, Masafumi Kubota, Tetsuya Ueda
  • Patent number: 6812101
    Abstract: A zirconium silicate layer 103 is formed on a silicon substrate 100, a zirconium oxide layer 102 is also formed on the zirconium silicate layer 103, and the zirconium oxide layer 102 is then removed, thereby forming a gate insulating film 104 made of the zirconium silicate layer 103.
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: November 2, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaru Moriwaki, Masaaki Niwa, Masafumi Kubota
  • Patent number: 6734451
    Abstract: On a silicon substrate is formed a silicon dioxide film and then hemispherical grains made of silicon, each having an extremely small diameter, are deposited thereon by LPCVD. After annealing the hemispherical grains, the silicon dioxide film is etched using the hemispherical grains as a first dotted mask, thereby forming a second dotted mask composed of the silicon dioxide film. The resulting second dotted mask is used to etch the silicon substrate to a specified depth from the surface thereof, thereby forming an aggregate of semiconductor micro-needles. Since the diameter of each of the semiconductor micro-needles is sufficiently small to cause the quantum size effects as well as has only small size variations, remarkable quantum size effects can be obtained. Therefore, it becomes possible to constitute a semiconductor apparatus with a high information-processing function by using the aggregate of semiconductor micro-needles (quantized region).
    Type: Grant
    Filed: October 22, 2002
    Date of Patent: May 11, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koji Eriguchi, Masafumi Kubota, Masaaki Niwa, Noboru Nomura
  • Publication number: 20040087124
    Abstract: An underlying insulting film of silicon oxide, a gate insulating film of hafnium oxide, a gate electrode of polysilicon and side walls of silicon oxide are formed above an element formation region of a semiconductor substrate. In the upper portion of the element formation region of the semiconductor substrate, source and drain areas and extension areas are formed by implantations of respective types. Thereafter, the scan speed of the semiconductor substrate and the pulse interval and the peak power of laser beam are adjusted to irradiate only the vicinity of the surface of the semiconductor substrate with laser beam for 0.1 second so that the vicinity of the surface of the semiconductor substrate has a temperature of 1150 to 1250° C. Thus, heat treatments for the gate insulating film and the source and drain areas are performed.
    Type: Application
    Filed: September 16, 2003
    Publication date: May 6, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Masafumi Kubota, Shigenori Hayashi
  • Patent number: 6667246
    Abstract: A substrate with a metal oxide film deposited thereon is annealed, and then the surface of the metal oxide film is exposed to a plasma, after which the metal oxide film is removed by wet-etching.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: December 23, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Riichiro Mitsuhashi, Masafumi Kubota, Shigenori Hayashi
  • Publication number: 20030173586
    Abstract: A zirconium silicate layer 103 is formed on a silicon substrate 100, a zirconium oxide layer 102 is also formed on the zirconium silicate layer 103, and the zirconium oxide layer 102 is then removed, thereby forming a gate insulating film 104 made of the zirconium silicate layer 103.
    Type: Application
    Filed: January 10, 2003
    Publication date: September 18, 2003
    Inventors: Masaru Moriwaki, Masaaki Niwa, Masafumi Kubota
  • Publication number: 20030104706
    Abstract: A substrate with a metal oxide film deposited thereon is annealed, and then the surface of the metal oxide film is exposed to a plasma, after which the metal oxide film is removed by wet-etching.
    Type: Application
    Filed: December 4, 2002
    Publication date: June 5, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Riichiro Mitsuhashi, Masafumi Kubota, Shigenori Hayashi