Patents by Inventor Masafumi Miyagawa

Masafumi Miyagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4610079
    Abstract: A method of dicing a semiconductor wafer in which a physical discontinuity is formed on the surface of the wafer on both sides of a dicing line to limit the spreading of cracks and chips generated during dicing. Thereafter, the semiconductor wafer is diced to separate the pellets.
    Type: Grant
    Filed: February 26, 1985
    Date of Patent: September 9, 1986
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Masahiro Abe, Masafumi Miyagawa, Hatsuo Nakamura, Toshio Yonezawa
  • Patent number: 4589004
    Abstract: A semiconductor device comprising a high voltage withstanding vertical MOSFET and a low voltage withstanding element both formed on a single chip. A buried layer of a high impurity concentration is formed in a region where the vertical MOSFET is formed, and another buried layer of a high impurity concentration is formed in a region where the low voltage withstanding element is formed. These buried layers have different thickness, whereby the series resistance of a circuit adjacent to the vertical MOSFET is reduced without lowering the withstand voltage of the vertical MOSFET.
    Type: Grant
    Filed: October 30, 1984
    Date of Patent: May 13, 1986
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Seiji Yasuda, Toshio Yonezawa, Shunichi Hiraki, Masafumi Miyagawa
  • Patent number: 4451303
    Abstract: A method for producing a semiconductor element which can form a deep P-type impurity region by a diffusion of aluminum. A porous alumina layer is first formed on a semiconductor substrate. Then, a diffusion-protective layer formed of a material having a large oxygen-diffusion-inhibiting ability such as Al.sub.2 O.sub.3 is formed on the porous alumina layer. Subsequently, aluminum ions are implanted in the porous alumina layer through the diffusion-protective layer. Thereafter, a heat treatment is performed to diffuse the aluminum of the aluminum ion-implanted region in the semiconductor substrate, and a P-type impurity region is formed. Alternatively, a porous alumina layer is formed on the semiconductor substrate, and an aluminum layer is then formed thereon. The diffusion-protective layer is formed on the aluminum layer, and a heat treatment is then performed, thereby diffusing the aluminum forming the aluminum layer in the semiconductor substrate, and a P-type impurity region is thus formed.
    Type: Grant
    Filed: January 5, 1983
    Date of Patent: May 29, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Shunichi Hiraki, Kiyoshi Kikuchi, Shigeo Yawata, Masafumi Miyagawa