Abstract: A method for processing a contrast picture image of a semiconductor element. The method comprises; a color grade number reducing processing that automatically reduces number of color grades of the contrast picture image of the semiconductor element, obtained from a device for analysis, in keeping with the contrast of the contrast picture image; an interconnect contrast extraction processing that classifies pixels contained in the contrast picture image, whose number of color grades has been reduced, in accordance with a preset contrast threshold value as reference, to extract an interconnect pattern fractionated into a plurality of number of contrasts; and a shift processing that removes noise contained in a contour portion of the interconnect pattern by shifting the contour portion; whereby an interconnect pattern contained in the contrast image of the semiconductor element obtained from the device for analysis is fractionated into a plurality of preset contrasts to be extracted.

Abstract: A semiconductor device failure analysis method and apparatus and a computer program for the method and apparatus are provided. The method includes: an observation image acquisition process of acquiring a voltage contrast image by charging an exposed conductive layer of a semiconductor device and irradiating the exposed conductive layer with charged particles; a wiring search process of searching for end points connected to the conductive layer based on design data; and a determination process of comparing voltage contrasts of three levels or more set in advance, one of which is set for a wiring depending on a state of an end point of the wiring, with the voltage contrast image acquired in the observation image acquisition process to determine consistency/inconsistency. Since three or more levels are set, for example, a short-circuit formed by a conductive layer connected to a transistor diffusion layer and another wiring can be identified.

Abstract: A failure analysis method for a semiconductor integrated circuit includes deriving a coordinate in a device coordinate system in analysis data for abnormal signal data included in the analysis data of a semiconductor integrated circuit, deriving a correspondence between a coordinate in the device coordinate system and a coordinate in a design coordinate system in design data of the semiconductor integrated circuit for a plurality of reference points in the semiconductor integrated circuit, deriving a coordinate conversion formula between the device coordinate system and the design coordinate system, deriving a position error between a coordinate in the device coordinate system converted by the coordinate conversion formula and a coordinate in the design coordinate system, and extracting a circuit related to an abnormal signal in the design data based on coordinates of the abnormal signal in the device coordinate system using the coordinate conversion formula and the position error.

Abstract: A method of analyzing of a semiconductor integrated circuit includes inspecting a physical defect in a semiconductor wafer, subjecting the semiconductor integrated circuit chip to a logic test and extracting a malfunctioning chip, analyzing a detected signal observed from the malfunctioning chip by an analyzer, obtaining the layer and coordinates of a circuit related the detected signal, collating the physical defect with the circuit, and identifying the physical defect associated with the circuit. The layer and coordinates of the circuit is extracted using design data. An inspection step identifying information is collated with the layer of the circuit, and an in-chip coordinates of the physical defect is collated with the coordinated of the circuit.

Abstract: A method for processing a contrast picture image of a semiconductor element. The method comprises: a color grade number reducing processing that automatically reduces number of color grades of the contrast picture image of the semiconductor element, obtained from a device for analysis, in keeping with the contrast of the contrast picture image; an interconnect contrast extraction processing that classifies pixels contained in the contrast picture image, whose number of color grades has been reduced, in accordance with a preset contrast threshold value as reference, to extract an interconnect pattern fractionated into a plurality of number of contrasts; and a shift processing that removes noise contained in a contour portion of the interconnect pattern by shifting the contour portion; whereby an interconnect pattern contained in the contrast image of the semiconductor element obtained from the device for analysis is fractionated into a plurality of preset contrasts to be extracted.

Abstract: Provided is a display method used for a display device that displays a design image and a pickup image in a superimposing manner, including: a distortion correction process of correcting distortion of the pickup image; an alignment process of aligning a position of the design image and a position of the pickup image; and a display process of displaying the design image and the pickup image in the superimposing manner. In the distortion correction process, the distortion of the pickup image is corrected so that a quadrangle formed by connecting four points on the pickup image becomes a rectangle in parallel with a vertical axis and a horizontal axis, the four points specified on the pickup image corresponding to four points on the design image which are connected to form a rectangle in parallel with the vertical axis and the horizontal axis.

Abstract: A semiconductor device failure analysis method and apparatus and a computer program for the method and apparatus are provided. The method includes: an observation image acquisition process of acquiring a voltage contrast image by charging an exposed conductive layer of a semiconductor device and irradiating the exposed conductive layer with charged particles; a wiring search process of searching for end points connected to the conductive layer based on design data; and a determination process of comparing voltage contrasts of three levels or more set in advance, one of which is set for a wiring depending on a state of an end point of the wiring, with the voltage contrast image acquired in the observation image acquisition process to determine consistency/inconsistency. Since three or more levels are set, for example, a short-circuit formed by a conductive layer connected to a transistor diffusion layer and another wiring can be identified.

Abstract: There are provided a signal detection process that derives coordinates in a device coordinate system in analysis data for abnormal signal data included in the analysis data of a semiconductor integrated circuit obtained from a semiconductor inspection apparatus; a coordinate conversion process that derives a correspondence between a coordinate in the device coordinate system and a coordinate in a design coordinate system in the design data of the semiconductor integrated circuit for a plurality of reference points in the semiconductor integrated circuit, and that derives a coordinate conversion formula between the device coordinate system and the design coordinate system; an error calculation process that derives a position error between a coordinate in the device coordinate system converted by the coordinate conversion formula and a coordinate in the design coordinate system; and a circuit extraction process that extracts a circuit related to the abnormal signal in the design data based on the coordinates of

Abstract: A failure diagnosing method of logic circuits includes generating failure candidate data for logic circuits based on failure diagnosis data obtained from the logic circuits by using a failure diagnosis tool; and inputting the failure candidate data for the logic circuits. A predetermined data is extracted from each of the failure candidate data for the logic circuits. Failures of the logic circuits are diagnosed by collecting a name of each of the failure candidate data from the predetermined data and the number of failure candidate data; and the collected data are outputted on a display unit.

Abstract: Provided is a display method used for a display device that displays a design image and a pickup image in a superimposing manner, including: a distortion correction process of correcting distortion of the pickup image; an alignment process of aligning a position of the design image and a position of the pickup image; and a display process of displaying the design image and the pickup image in the superimposing manner. In the distortion correction process, the distortion of the pickup image is corrected so that a quadrangle formed by connecting four points on the pickup image becomes a rectangle in parallel with a vertical axis and a horizontal axis, the four points specified on the pickup image corresponding to four points on the design image which are connected to form a rectangle in parallel with the vertical axis and the horizontal axis.

Abstract: A method of analyzing of a semiconductor integrated circuit includes inspecting a physical defect in a semiconductor wafer, subjecting the semiconductor integrated circuit chip to a logic test and extracting a malfunctioning chip, analyzing a detected signal observed from the malfunctioning chip by an analyzer, obtaining the layer and coordinates of a circuit related the detected signal, collating the physical defect with the circuit, and identifying the physical defect associated with the circuit. The layer and coordinates of the circuit is extracted using design data. An inspection step identifying information is collated with the layer of the circuit, and an in-chip coordinates of the physical defect is collated with the coordinated of the circuit.

Abstract: A failure diagnosing method of logic circuits includes generating failure candidate data for logic circuits based on failure diagnosis data obtained from the logic circuits by using a failure diagnosis tool; and inputting the failure candidate data for the logic circuits. A predetermined data is extracted from each of the failure candidate data for the logic circuits. Failures of the logic circuits are diagnosed by collecting a name of each of the failure candidate data from the predetermined data and the number of failure candidate data; and the collected data are outputted on a display unit.