Abstract: A semiconductor device includes a semiconductor chip, which includes a substrate, a multilayer interconnect layer formed over the substrate, a first cell column disposed along an edge of the substrate in a plan view, the first cell column having a first I/O cell and a first power supply cell, second cell column disposed along the first cell column in plan view, the second cell column having a second I/O cell, a first pad supplying a first supply voltage to the first power supply cell, a first voltage supply wire disposed over the first cell column, a second voltage supply wire disposed over the second cell column, and a first connection wire crossing the first voltage supply wire and the second voltage supply wire.

Abstract: A semiconductor device includes a multilayer interconnect layer formed over a substrate, an outer peripheral cell column disposed along an edge of the substrate in a plan view, the outer peripheral cell column including a first I/O cell, first and second inner peripheral cell columns formed at an inner peripheral side of the outer peripheral cell column, the first and second inner peripheral cell columns including a second I/O cell, and signal interconnects for forming an internal circuit of the semiconductor device, arranged between the first inner peripheral cell column and the second inner peripheral cell column.

Abstract: A semiconductor device includes a semiconductor chip, the semiconductor chip including a substrate, a multilayer interconnect layer formed over the substrate, an outer peripheral cell column disposed along an edge of the substrate in a plan view, the outer peripheral cell column having at least one first I/O cell, and an inner peripheral cell column formed at an inner peripheral side of the outer peripheral cell column, the inner peripheral cell column having at least one second I/O cell.

Abstract: A semiconductor device includes a semiconductor chip, the semiconductor chip including a substrate, a multilayer interconnect layer formed over the substrate, an outer peripheral cell column disposed along an edge of the substrate in a plan view, the outer peripheral cell column having at least one first I/O cell, and an inner peripheral cell column formed at an inner peripheral side of the outer peripheral cell column, the inner peripheral cell column having at least one second I/O cell.

Abstract: A potential-supply connection interconnect is provided in a multilayer interconnect layer. The potential supply connection interconnect overlaps some cell of I/O cells in the outer peripheral cell column and some cell of I/O cells in the inner peripheral cell column in a plan view. The potential-supply connection interconnect connects a power potential supply interconnect located below the outer peripheral cell column to a power potential supply interconnect located below the inner peripheral cell column and also connects a ground potential supply interconnect located below the outer peripheral cell column to a ground potential supply interconnect located below the inner peripheral cell column.

Abstract: A semiconductor integrated circuit free from increase in chip area or significant reversion in designing is provided. The semiconductor integrated circuit includes: IO buffers arrayed in line; pad coupling wirings respectively arrayed in correspondence with the IO buffers; and IO buffer switching wirings respectively arrayed in line in correspondence with the IO buffers, set in a layer different from those of the IO buffers and the pad coupling wirings so that they overlap with part of the corresponding pad coupling wirings, and extended to other pad coupling wirings adjacent to the corresponding pad coupling wirings. Each of the IO buffer switching wirings is formed in an identical shape so that it is not short-circuited to adjacent other IO buffer switching wirings. The IO buffers are electrically coupled with the corresponding IO buffer switching wirings in the same positions.

Abstract: A potential-supply connection interconnect is provided in a multilayer interconnect layer. The potential supply connection interconnect overlaps some cell of I/O cells in the outer peripheral cell column and some cell of I/O cells in the inner peripheral cell column in a plan view. The potential-supply connection interconnect connects a power potential supply interconnect located below the outer peripheral cell column to a power potential supply interconnect located below the inner peripheral cell column and also connects a ground potential supply interconnect located below the outer peripheral cell column to a ground potential supply interconnect located below the inner peripheral cell column.

Abstract: A test circuit is capable of easily testing the standby function of an interface block. The test circuit is used for the interface block disposed on a semiconductor integrated circuit which is switched between a standby mode and a non-standby mode and conducting interfacing between the semiconductor integrated circuit and the outside in the non-standby mode, generating a fixed voltage and outputting the same to a corresponding signal line in the standby mode. The test circuit is disposed on the semiconductor integrated circuit and generates a current in accordance with the voltage level of the signal line in the standby mode.

Abstract: A semiconductor integrated circuit free from increase in chip area or significant reversion in designing is provided. The semiconductor integrated circuit includes: IO buffers arrayed in line; pad coupling wirings respectively arrayed in correspondence with the IO buffers; and IO buffer switching wirings respectively arrayed in line in correspondence with the IO buffers, set in a layer different from those of the IO buffers and the pad coupling wirings so that they overlap with part of the corresponding pad coupling wirings, and extended to other pad coupling wirings adjacent to the corresponding pad coupling wirings. Each of the IO buffer switching wirings is formed in an identical shape so that it is not short-circuited to adjacent other IO buffer switching wirings. The IO buffers are electrically coupled with the corresponding IO buffer switching wirings in the same positions.