Abstract: A semiconductor device structure includes a region of semiconductor material with a first major surface and an opposing second major surface. A contact structure is disposed in a first portion of the region of semiconductor material and includes a tub structure extending from adjacent a first portion of the first major surface. A plurality of structures comprising portions of the region of semiconductor material extend outward from a lower surface of the tub structure. In some embodiments, the plurality of structures comprises a plurality of free-standing structures. A conductive material is disposed within the tub structure and laterally surrounding the plurality of structures. In one embodiment, the contact structure facilitates the fabrication of a monolithic series switching diode structure having a low-resistance substrate contact.

Abstract: A semiconductor device structure includes a region of semiconductor material with a first major surface and an opposing second major surface. A contact structure is disposed in a first portion of the region of semiconductor material and includes a tub structure extending from adjacent a first portion of the first major surface. A plurality of structures comprising portions of the region of semiconductor material extend outward from a lower surface of the tub structure. In some embodiments, the plurality of structures comprises a plurality of free-standing structures. A conductive material is disposed within the tub structure and laterally surrounding the plurality of structures. In one embodiment, the contact structure facilitates the fabrication of a monolithic series switching diode structure having a low-resistance substrate contact.

Abstract: A transistor structure that improves ESD withstand voltages is offered. A high impurity concentration drain layer is formed in a surface of an intermediate impurity concentration drain layer at a location separated from a drain-side end of a gate electrode. And a P-type impurity layer is formed in a surface of a substrate between the gate electrode and the high impurity concentration drain layer so as to surround the high impurity concentration drain layer. When a parasitic bipolar transistor is turned on by an abnormal surge, electrons travel from a source electrode to a drain electrode. Here, electrons travel dispersed in the manner to avoid a vicinity X of the surface of the substrate and travel through a deeper path to the drain electrode as indicated by arrows in FIG. 4.

Abstract: In a semiconductor device, a region under a pad electrode with a bump can be utilized efficiently and a large amount of force is prevented from applying locally to a semiconductor substrate under the bump when the semiconductor device is mounted. A first layer metal wiring is formed on the semiconductor substrate. A pad electrode is formed on the first layer metal wiring through an interlayer insulation film. The pad electrode is connected with the first layer metal wiring through a via hole that is formed in the interlayer insulation film. A protection film is formed on the pad electrode. The protection film has an opening to expose the pad electrode and an island-shaped protection film formed in the opening. An Au bump connected with the pad electrode through the opening in the protection film is formed on the pad electrode. The via hole is formed under the island-shaped protection film, and incompletely filled with a portion of the pad electrode.

Abstract: In a semiconductor device, a region under a pad electrode with a bump can be utilized efficiently and a large amount of force is prevented from applying locally to a semiconductor substrate under the bump when the semiconductor device is mounted. A first layer metal wiring is formed on the semiconductor substrate. A pad electrode is formed on the first layer metal wiring through an interlayer insulation film. The pad electrode is connected with the first layer metal wiring through a via hole that is formed in the interlayer insulation film. A protection film is formed on the pad electrode. The protection film has an opening to expose the pad electrode and an island-shaped protection film formed in the opening. An Au bump connected with the pad electrode through the opening in the protection film is formed on the pad electrode. The via hole is formed under the island-shaped protection film, and incompletely filled with a portion of the pad electrode.

Abstract: A transistor structure that improves ESD withstand voltages is offered. A high impurity concentration drain layer is formed in a surface of an intermediate impurity concentration drain layer at a location separated from a drain-side end of a gate electrode. And a P-type impurity layer is formed in a surface of a substrate between the gate electrode and the high impurity concentration drain layer so as to surround the high impurity concentration drain layer. When a parasitic bipolar transistor is turned on by an abnormal surge, electrons travel from a source electrode to a drain electrode. Here, electrons travel dispersed in the manner to avoid a vicinity X of the surface of the substrate and travel through a deeper path to the drain electrode as indicated by arrows in FIG. 4.

Abstract: A withstand voltage against electrostatic discharge of a high voltage MOS transistor is improved. An N?-type drain layer is not formed under an N+-type drain layer, while a P+-type buried layer is formed in a region under the N+-type drain layer. A PN junction of high impurity concentration is formed between the N+-type drain layer and the P+-type buried layer. In other words, a region having low junction breakdown voltage is formed locally. The surge current flows through the PN junction into the silicon substrate before the N?-type drain layer below a gate electrode is thermally damaged. Hence, the ESD withstand voltage is improved.

Abstract: A withstand voltage against electrostatic discharge of a high voltage MOS transistor is improved. An N?-type drain layer is not formed under an N+-type drain layer, while a P+-type buried layer is formed in a region under the N+-type drain layer. A PN junction of high impurity concentration is formed between the N+-type drain layer and the P+-type buried layer. In other words, a region having low junction breakdown voltage is formed locally. The surge current flows through the PN junction into the silicon substrate before the N?-type drain layer below a gate electrode is thermally damaged. Hence, the ESD withstand voltage is improved.

Abstract: A manufacturing method of this invention has an ion-implantation process for threshold voltage adjustment of an MOS transistor, including a process to form a first well of an opposite conductivity type in a substrate of one conductivity type, to form a second well of the opposite conductivity type having higher impurity concentration than that in the first well, under a region where a thin gate insulation film is formed, to form gate insulation films on the first well and the second well, each having a different thickness, to ion-implant first impurities of the one conductivity type into the wells of the opposite conductivity type under the condition that the impurities penetrate the gate insulation films of different thicknesses and to ion-implant second impurities of the one conductivity type into the second well of the opposite conductivity type under the condition that the second impurities penetrate the thin gate insulation film but do not penetrate the thick gate insulation film.

Abstract: A withstand voltage against electrostatic discharge of a high voltage MOS transistor is improved. An N−-type drain layer is not formed under an N+-type drain layer, while a P+-type buried layer is formed in a region under the N+-type drain layer. A PN junction of high impurity concentration is formed between the N+-type drain layer and the P+-type buried layer. In other words, a region having low junction breakdown voltage is formed locally. The surge current flows through the PN junction into the silicon substrate before the N−-type drain layer below a gate electrode is thermally damaged. Hence, the ESD withstand voltage is improved.

Abstract: A withstand voltage against electrostatic discharge of a high voltage MOS transistor is improved. An N−-type drain layer is not formed under an N+-type drain layer, while a P+-type buried layer is formed in a region under the N+-type drain layer. A PN junction of high impurity concentration is formed between the N+-type drain layer and the P+-type buried layer. In other words, a region having low junction breakdown voltage is formed locally. The surge current flows through the PN junction into the silicon substrate before the N−-type drain layer below a gate electrode is thermally damaged. Hence, the ESD withstand voltage is improved.

Abstract: A manufacturing method of this invention has an ion-implantation process for threshold voltage adjustment of an MOS transistor, including a process to form a first well of an opposite conductivity type in a substrate of one conductivity type, to form a second well of the opposite conductivity type having higher impurity concentration than that in the first well, under a region where a thin gate insulation film is formed, to form gate insulation films on the first well and the second well, each having a different thickness, to ion-implant first impurities of the one conductivity type into the wells of the opposite conductivity type under the condition that the impurities penetrate the gate insulation films of different thicknesses and to ion-implant second impurities of the one conductivity type into the second well of the opposite conductivity type under the condition that the second impurities penetrate the thin gate insulation film but do not penetrate the thick gate insulation film.

Abstract: The improved method of development is implemented with an automatic processor for developing presensitized offset printing plates with a substantially virgin aqueous solution that contains an alkali silicate and that is supplied for each printing plate, said aqueous solution containing calcium ions in an amount of up to 10 mg/L. The improved developing apparatus comprises a means of mixing a concentrated developing solution with diluent water to prepare a working solution and a means of applying the working solution onto the surface of a presensitized offset printing plate being transported. The apparatus is characterized by further including a mechanism that performs ion-exchange on the diluent water before it is mixed with the concentrated developing solution.

Abstract: Disclosed is a photosensitive composition comprising a diazo resin and a polymeric compound containing a structural unit represented by the following formula (I) in the molecule: ##STR1## wherein J represents a divalent linking group and n is 0 or 1. Disclosed is also a photosensitive lithographic printing using the photosensitive composition.

Abstract: A developing solution of an imagewise exposed, presensitized offset printing plate is disclosed. The developing solution has a pH of at least 12.5, and contains a low content of a silicate in an amount of up to 1.0 wt % as SiO.sub.2, a surfactant in an amount of 0.01 to 10 wt %, an aromatic carboxylic acid in an amount of 0.1 to 10 wt %, and an amine compound represented by the following general formula (I) in an amount of 0.1 to 10 wt %:R.sub.1 --N(R.sub.2)--J--OH (I)wherein R.sub.1 and R.sub.2 are each independently a hydrogen atom, a group --C.sub.2 H.sub.4 OH or a group --C.sub.3 H.sub.6 OH; and J is a group --C.sub.2 H.sub.4 -- or --C.sub.3 H.sub.6 --.

Abstract: Disclosed are a method and an apparatus for processing with a developing solution repeatedly used, both an imagewise exposed, positive-working presensitized lithographic printing plate and an imagewise exposed negative-working presensitized lithographic printing plate. The plates each comprise an aluminum support and a light-sensitive layer formed thereon. A replenishing solution is added to the developing solution to compensate for the degradation of the developing solution brought about by development and/or by carbon dioxide in the air. The method comprises the steps of; measuring a reflection density of the light-sensitive layer of the printing plates to discriminate the type of the printing plate, selecting a predetermined developing condition according to the discriminated type of the printing plate, and developing the printing plates according to the selected developing condition.

Abstract: A method of developing a waterless light-sensitive lithographic printing plate having a support and, provided thereon, a light-sensitive layer comprising a diazo resin and a silicone gum layer with a developer is disclosed. The developer comprises an organic carboxylic acid or salt thereof, water, and at least one of a sulfite and a surfactant.

Abstract: There are disclosed an aqueous alkaline developer for light-sensitive lithographic printing plate commonly processing a negative-type light-sensitive lithographic printing plate having a light-sensitive layer containing a diazo compound and a positive-type light-sensitive lithographic printing plate having a light-sensitive layer containing an o-quinonediazide compound, which comprises containing an alkali agent, 0.1 to 10% by weight of a water-soluble reducing agent, a sodium, potassium or ammonium salt of an organic carboxylic acid, and a non-ionic or cationic surfactant, and having a pH in the range of 12.5 to 13.5, and also a developer composition for light-sensitive material, which comprises an aqueous solution containing a compound represented by the formula (I) shown below: ##STR1## wherein R.sub.1 represents an alkyl group or an alkoxy group each having 2 to 5 carbon atoms, or a hydroxyalkyl group having 2 to 5 carbon atoms; and R.sub.

Abstract: An apparatus for processing an imagewise exposed pre-sensitized lithographic printing plate which entails uniformly applying a desired amount of developer, that has not been substantially used to the surface of the printing plate by a developer supply member comprised of two plates and having a slit at the lowermost portion thereof which contacts the surface of the printing plate, and then transferring the plate containing the developer to a developer storage tank, immersing the plate in the developer storage tank, and removing the developer from the plate.

Abstract: A photosensitive composition, comprising a photosensitive diazo compound and a polymeric binder, wherein the diazo compound has a polymerizable unsaturated bond in the molecule.