Abstract: One exemplary embodiment includes a semiconductor chip that has a rectangle principal surface including a first and a second side that oppose each other. A first and a second semiconductor element, and a first and a second wire are formed on the principal surface. The first wire is formed from the first side to reach the second side, and coupled to the first semiconductor element. The second wire is formed to contact at least the first wire, and coupled to the second semiconductor element. Further, an edge part of the first wire on the second side and an edge part of the second wire on the first side are placed to substantially position on a common straight line which is vertical to the first and the second sides.

Abstract: One exemplary embodiment includes a semiconductor chip that has a rectangle principal surface including a first and a second side that oppose each other. A first and a second semiconductor element, and a first and a second wire are formed on the principal surface. The first wire is formed from the first side to reach the second side, and coupled to the first semiconductor element. The second wire is formed to contact at least the first wire, and coupled to the second semiconductor element. Further, an edge part of the first wire on the second side and an edge part of the second wire on the first side are placed to substantially position on a common straight line which is vertical to the first and the second sides.

Abstract: In order to improve verification performance for the cell hierarchy in a gate array LSI layout, and accurately, efficiently verify the hierarchy at a high speed, this invention relates to a hierarchy verification method and apparatus for an LSI layout in which, in verifying the cell hierarchy in the gate array LSI layout, input gate array LSI layout data is divided into a top cell data portion and a function block cell data portion, the top cell data portion is mapped while leaving only a wiring figure in an underlying cell, an underlying cell of the function block cell data portion that is pasted while maintaining a relative positional relationship with a laid function block cell is mapped, and each figure layout of the cell hierarchy is verified using the obtained top cell data and function block cell data.