Abstract: A method of forming a trench buried wiring on a semiconductor device. The method includes the steps of: forming a trench in a first insulating film formed on a semiconductor substrate, by using as a mask a photoresist layer, the trench having substantially an upright step; depositing a first electrode material on the surface of the photoresist layer and on the bottom of the trench, while leaving the photoresist layer; removing the photoresist layer and the first electrode material on the photoresist layer while leaving the first electrode material only on the bottom of the trench; and filling a second electrode material in the trench to form a composite electrode with the second electrode material being superposed on the first electrode material.

Abstract: Measurement of temperature - internal stress characteristics of an Al thin film formed on an Si substrate is performed. The amount of an impurity or impurities mixed in the thin f ilm can be obtained in accordance with the measured characteristics. A migration start temperature of Al atoms in the thin film in the characteristics obtained when the temperature is increased is fed back as information to the thin film formation step, thereby controlling an impurity amount in an atmosphere for forming the thin film.

Abstract: A semiconductor device has a passivation layer including a polyimide film. Argon ions are implanted in the polyimide film to convert it into an electrically stable insulating film.

Abstract: In a method of manufacturing a semiconductor device according to the present invention, a given position of a thermal oxide film formed on a monocrystalline silicon layer is opened to expose a surface of the monocrystalline silicon layer to serve as a getter site, a polycrystalline silicon layer is deposited on the thermal oxide film and the surface of the monocrystalline silicon layer, and the polycrystalline silicon layer is oxidized to convert the surface of the monocrystalline silicon layer directly contacting the polycrystalline silicon layer into an oxide film by thermal oxidation. That is, the position of interface between the oxide film and the monocrystalline silicon layer is shifted into the original monocrystalline silicon layer. During thermal oxidation of the polycrystalline silicon layer, a plurality of crystal defects to serve as getter sites are generated deeper than those generated by a conventional implagetter method in the monocrystalline silicon layer.

Abstract: A method of manufacturing a semiconductor device comprising the steps of preparing a semiconductor substrate on which a first insulation film is formed, forming a first conductive layer on the first insulation film, forming a hillock of the first conductive layer, forming a second insulation film on the structure, removing that portion of the second insulation film, in self-align with the hillock, which is on the hillock, thereby forming a contact hole leading to the first conductive layer, and forming on the structure a second conductive layer extending into the contact hole and contacting the first conductive layer.

Abstract: A method of manufacturing a semiconductor device, comprising the steps of sequentially forming a buried region and an epitaxial layer on a major surface of a semiconductor substrate, forming a conductive layer along an annular trench extending to the buried region, filling the annular trench with an insulating material and forming a functional element in said epitaxial layer surrounded by said buried region and said insulating material within said annular trench. In this method, the step of forming the conductive layer along the annular trench is carried out by the steps of forming an annular trench extending through said buried region, and depositing a conductive layer on only a side wall surface of said annular trench.

Abstract: A semiconductor device with a bonding section comprising a semiconductor substrate, a silicon layer formed on the semiconductor substrate with a first insulating layer interposed therebetween, and a bonding pad formed on the silicon layer with a second insulating layer interposed therebetween. The silicon layer has substantially the same size as the bonding pad. When a lead line is bonded to the bonding pad, the silicon layer lessens the stress caused by the bonding.

Abstract: A method for planarizing the surface of an insulation layer deposited on a first interconnection layer to allow a second interconnection layer deposited thereon without causing a breakage of the second interconnection layer. This method is characterized in that at least two insulation films, different in etching characteristics each other, are first formed on the first interconnection layer, and then a resist layer is deposited on the second insulating film. Subsequently, a portion of the resist layer is etched to expose the top surface of the second insulating film, and the second insulating film is selectively and anisotropically etched using the remaining resist layer as a mask. After removing the first insulating film and the remaining resist mark, a third insulating film is deposited to a thickness sufficient to make flat the surface thereof.

Abstract: A semiconductor device having a multilayer wiring structure which comprises a semiconductor substrate, a first wiring layer deposited on said substrate, and a second wiring layer deposited on said first wiring layer with insulating layers disposed therebetween, wherein the insulating interlayer consists of an inorganic insulating layer and a polyimide-based resin film overlying the inorganic insulating layer. The thickness ratio of the polyimide-based resin film to the inorganic insulating film ranges from 0.1 to 0.5. A method of manufacturing a semiconductor device of a multilayer wiring structure wherein an opening is formed in the insulating interlayer to have a small step.

Abstract: A semiconductor device is disclosed which includes a multilayer formed of a hard inorganic main insulation film and a soft subinsulation film as insulation interlayers, and a hard inorganic insulation film as a final passivation film. The final passivation film is directly deposited on the hard inorganic main insulation film of the multilayer.

Abstract: A semiconductor device is disclosed which includes a semiconductor substrate; a metal wiring layer comprising an Al alloy formed on the surface of this substrate; and an alumina layer covering this metal layer and containing at least one metal selected from the group consisting of Cu, Mg, Ni, Cr, Mn, Ti and Y. A method for manufacturing such a semiconductor device is also disclosed.

Abstract: A metallization structure having a substantially flat surface can be formed on a semiconductor substrate by forming first and second insulating layers on the substrate. The second insulating layer is selectively removed to form grooves therein. Then, a metallic material layer is conformably formed. The metallic layer has grooves corresponding to the grooves of the second insulating layer. A flowable polymer is applied to the surface of the resultant structure to form a layer having a flat surface. The polymer layer and the metallic layer are sequentially ion-etched to expose the second insulating layer. Thus, the metallization structure constituted by the remaining metallic layer and the second insulating layer is formed to have a flat surface.

Abstract: A semiconductor memory device is disclosed which comprises:a semiconductor substrate of n conductivity type;source and drain regions of p.sup.+ conductivity type formed in the substrate;a first gate insulation film of silicon dioxide (SiO.sub.2) formed on the substrate; anda second gate insulation film of silicon carbide (SiC) formed on the first gate insulation film.

Abstract: A system is adapted to etch an aluminium film on a semiconductor wafer into a predetermined pattern by immersing the film in an etching solution. The system comprises a voltage detecting circuit for detecting a voltage created between a platinum electrode and the aluminium film on the semiconductor wafer which are immersed in the etching solution, a comparator for comparing a reference voltage with the voltage detected by the voltage detecting circuit to produce an output signal, and a timer for starting a time count operation upon receipt of the output signal from the comparator and for producing an etching completion signal when it continuously receives the output signal from the comparator for a predetermined time period.

Abstract: A semiconductor device is disclosed which includes a semiconductor substrate; a metal wiring layer comprising an Al alloy formed on the surface of this substrate; and an alumina layer covering this metal layer and containing at least one metal selected from the group consisting of Cu, Mg, Ni, Cr, Mn, Ti and Y. A method for manufacturing such a semiconductor device is also disclosed.

Abstract: A method for manufacturing a semiconductor device having a high breakdown voltage and a high reliability, comprises (a) forming on a semiconductor substrate an insulating layer having a diffusion window; (b) forming an impurity-doped poly-silicon layer on the insulating layer and on that portion of the semiconductor substrate which is exposed through the diffusion window; (c) forming an undoped poly-silicon layer on the impurity-doped poly-silicon layer; (d) thermally oxidizing the substrate with the insulating layer, impurity-doped poly-silicon layer and undoped poly-silicon layer, thus diffusing the impurity from the impurity-doped poly-silicon layer into the semiconductor substrate through the diffusion window and converting the undoped poly-silicon layer to a silicon oxide layer; (e) forming on the silicon oxide layer an oxidation-resisting mask layer in a desired pattern; and (f) thermally oxidizing the substrate with the insulating layer, impurity-doped poly-silicon layer, silicon oxide layer and mask l

Abstract: Disclosed is a method of producing a semiconductor device, comprising the steps of (a) forming a first insulating layer consisting of a lower silicon oxide film and an upper slicon nitride film on the surface of a semiconductor substrate, (b) forming a second insulating layer consisting of silicon oxide on the first insulating layer, (c) forming a third insulating layer consisting of silicon nitride on the second insulating layer, (d) selectively removing the third insulating layer so as to form a mask used for forming a hole for an interconnection electrode, (e) etching away the exposed portion of the second insulating layer by using the mask so as to form the hole for the interconnection electrode, (f) forming a conductive material layer on the entire surface of the structure obtained by step (e), a contact hole formed in the first insulating layer after step (a) or (e) being filled with the conductive material so as to allow the conductive material layer disposed on the first insulating layer to be connect

Abstract: A semiconductor device comprising a fluorine ion implantation region which is selectively formed in a semiconductor region and further activated. The fluorine ion implantation region is adapted for use as a high resistance layer or electrical isolation layer.

Abstract: There are provided a semiconductor device having alternately layered insulating and conductive layers on the major surface of a semiconductor body and the process for manufacturing the semiconductor device. In the manufacturing process, the conductive layers other than the conductive layer finally formed are each formed to be a laminate including at least two metal layers of which the etching rates are different. The photo-engraving process follows this step. In the lamina, the metal layer closer to the semiconductor body has a lower etching rate than that of the metal layer formed thereover. In the semiconductor device, the conductive layer other than that disposed furthest away from the semiconductor body has its side wall diverged to widen toward the semiconductor body.