Abstract: A method for optimizing a pattern generation program used in a signal generator comprising a generator for generating a signal pattern based on a pattern generation program, a memory for storing the signal pattern, and an output for outputting on a predetermined cycle the signal pattern stored by the memory, this optimizing method comprising an evaluation step for evaluating for each command of the pattern generation program whether it is necessary to develop the command in question of the program and a development step for developing the command.

Abstract: A current/charge-voltage convert circuit having an operational amplifier and a capacitor connected between the input terminal and the output terminal of the operational amplifier, this current/charge-voltage convert circuit characterized in that it comprises a first pair of diodes connected in mutually opposing directions to this input terminal, a second pair of diodes connected in the opposite direction of this first pair of diodes to the respective other terminal of this first pair of diodes, a pair of current sources connected in mutually opposing directions to the respective other terminal of this first pair of diodes, a pair of switches connected to the respective other terminal of this first pair of diodes, and resistors connected between the respective other terminal of this second pair of diodes.

Abstract: A breather chamber structure of an internal combustion engine in which condensation of vapor within the breather chamber is prevented, the number of required parts is small, the space efficiency is superior and enlargement of the whole engine can be avoided is provided. In an internal combustion engine having auxiliary machinery attached to a side wall of a cylinder block (3) by means of an auxiliary machinery bracket (10), a breather chamber (20) is formed by the side wall of the cylinder block (3) and the auxiliary machinery bracket (10) between the side wall and the bracket, and a cooling water passage (40), (41) is formed on at least one of the side wall of the cylinder block (3) and the auxiliary machinery bracket (10) swelling in the breather chamber (20).

Abstract: An auxiliary part mounting bracket for an in-line multi-cylinder engine. An oil pump, an auto-tensioner, an alternator, a water pump and a compressor are preassembled on the auxiliary part mounting bracket to form an assembly. This assembly is fixed to a side of the engine cylinder block by six bolts. One bolt is threadedly inserted into the cylinder block through a space defined between the upper oil pump and auto-tensioner and the lower alternator and water pump; two bolts are threadedly inserted into the cylinder block through a space defined between the upper positioned alternator and water pump and the lower positioned compressor. Thus, it is possible to enhance the assembling operation, when the plurality of auxiliary parts are fixed to an engine body through the auxiliary part mounting bracket.

Abstract: The present invention is intended to provide a testing and measuring apparatus for accurately and quickly calibrating the input and output timing of a plurality of test signal patterns and voltage levels. The invention also offers a method used for the calibration. The apparatus is equipped with a plurality of units (timing vector generators) each having a timing-generating circuit (a capture timing generator) and an external common reference timing circuit (a golden edge generator) outside the units. Each unit comprises: (1) a timing comparator circuit (a capture comparator) for comparing the timing each of the timing-generating circuits with the timing of the reference timing circuit to determine whether the former timing leads or lags the latter timing; and (2) a counter circuit which counts a number of comparisons made by the comparator circuit until their sequential relation has been reversed.

Abstract: A timing adjustment circuit consists of a delay circuit made from n delay elements (n is an integer of 2 or more) connected in series, with which an input signal p0 is delayed in succession by each delay element, in order to generate respective delay-signals p1, . . . , pn, and a selection circuit with which any one of input signals p0 and aforementioned respective delay signals p1, . . . , pn are selected by n+1 number of selection signals s0, . . . , sn. The selection circuit comprises a selection-signal generation circuit, a selection gate circuit, a selection-signal holding circuit and a delay-signal holding circuit. The selection-signal generation circuit generates selection signals s0, . . . , sn before input signal p0 is input. The selection-signal holding circuit holds selection-signals s0, . . . , sn from the selection-signal generation circuit until the active edge of p0, . . . , pn reaches each selection gate. The delay-signal holding circuit comprises n delay-signal holding elements.

Abstract: A system and method for compensating in real time the dynamic power variation of a computer chip containing CMOS devices is provided. The present invention functions to control the temperature variations on the chip thus eliminating the drift to analog signals associated with CMOS devices. The present invention controls the temperature with the use of a compensation heater located on the CMOS chip. The compensation heater is driven by a plurality of signals which act in harmony with one another to control the temperature on the chip when it becomes unstable. The system and method includes driving the compensation heater with a maximum dynamic power value to effectively maintain the temperature on the chip, evaluating the chip for temperature fluctuation, and compensating for the temperature fluctuation by driving the compensation heater with at least one compensation power value.

Abstract: A timing generator having no dead time and capable of altering a timing at any time. A rough timing pulse generating means suitably specifies one of a plurality of input clock pulses to generate a rough timing pulse for a desired timing. A timing vernier delays the rough timing pulse for a suitable delay time to generate a minute timing pulse. In a compensating circuit, the minute timing pulse is input to a delay circuit having one input terminal and plural output terminals, and one of the outputs at the output terminals for delay is selected by a multiplexer. When the multiplexer selects an output whose delay time is not zero, a next pulse can be input from the timing vernier to the dead time compensating circuit so that no dead time occurs.

Abstract: The present invention is a time vernier providing fine timing control of an input signal having coarse timing edges. The time vernier comprises a receiving means for receiving a value representing a desired time delay to be added to the coarse timing edge input. The desired time delay may have both fine and coarse delay aspects. The time vernier also comprises a first decoding means for decoding the fine delay aspect and generating fine delay control signals, as well as a second decoding means for decoding a coarse delay aspect and generating coarse delay control signals. A delay line is also included in the time vernier which has inputs to receive the input signal having coarse timing edges, the fine and coarse delay control signals, and a control voltage which automatically adjusts with temperature and power supply variations, so as to provide for temperature and power supply compensation. The delay line combines the fine and coarse delay signals to provide an output signal with fine timing edges.

Abstract: An apparatus for producing a high voltage comprising a high voltage output means operating on a system common voltage, and a floating power supply means operating on the output voltage from the high voltage output means which is at a floating common potential.