Abstract: A ferroelectric memory device comprising a plurality of ferroelectric memory elements. Each of the plurality of ferroelectric memory elements includes a channel layer containing a metal oxide, a ferroelectric layer in contact with the channel layer in which the ferroelectric layer contains hafnium oxide, a first gate electrode facing the channel layer via the ferroelectric layer, an insulating layer facing the ferroelectric layer via the channel layer; and a second gate electrode facing the channel layer via the insulating layer.

Abstract: A ferroelectric memory device has a three-dimensional stacked structure with multiple ferroelectric memory elements arranged in series. The ferroelectric memory device has a semiconductor member having a columnar shape including a metal oxide, a ferroelectric layer containing hafnium oxide and surrounding the semiconductor member in contact with a side surface of the semiconductor member, and a plurality of gate electrodes arranged along a longitudinal direction of the semiconductor member and facing a side surface of the semiconductor member through the ferroelectric layer. The semiconductor member is a continuous member from its outer periphery to its central axis.

Abstract: A three-dimensional array device with multiple layers in height direction includes a first two-dimensional array circuit located in a first layer; and a second two-dimensional array circuit located in a second layer adjacent to the first layer and overlapped in a plan view with the first two-dimensional array circuit. Each of the first two-dimensional array circuit and the second two-dimensional array circuit has a first wiring group, an input part that inputs signals to the first wiring group, a second wiring group that intersects the first wiring group and an output part that outputs signals from the second wiring group. The output part in the first two-dimensional array circuit is overlapped in a plan view on the input part in the second two-dimensional array circuit and is connected in a signal transferable manner.

Abstract: A ferroelectric memory device comprising a plurality of ferroelectric memory elements. Each of the plurality of ferroelectric memory elements includes a channel layer containing a metal oxide, a ferroelectric layer in contact with the channel layer in which the ferroelectric layer contains hafnium oxide, a first gate electrode facing the channel layer via the ferroelectric layer, an insulating layer facing the ferroelectric layer via the channel layer; and a second gate electrode facing the channel layer via the insulating layer.

Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

Abstract: A method of forming a self-forming spacer using oxidation. The self-forming spacer may include forming a fin field effect transistor on a substrate, the fin field effect transistor includes a gate on a fin, the gate is perpendicular to the fin; forming a gate spacer on the gate and a fin spacer on the fin, the gate spacer and the fin spacer are formed in a single step by oxidizing an exposed surface of the gate and an exposed surface of the fin; and removing the fin spacer from the fin.

Abstract: A clamp apparatus including two pairs of first and second clamp arms, which are supported rotatably with respect to a body and are disposed mutually in parallel. First and second cam members including respective cam surfaces are provided on ends of the first and second clamp arms. The first cam members are pressed by rollers upon lowering of a block body under a driving action of a first cylinder that makes up a drive unit. The first clamp arms are rotated to assume a clamped state. The second cam members are pressed by rollers upon lowering of a block body under a driving action of a second cylinder of the drive unit, whereby the second clamp arms are rotated to assume a clamped state.

Abstract: A method of forming a self-forming spacer using oxidation. The self-forming spacer may include forming a fin field effect transistor on a substrate, the fin field effect transistor includes a gate on a fin, the gate is perpendicular to the fin; forming a gate spacer on the gate and a fin spacer on the fin, the gate spacer and the fin spacer are formed in a single step by oxidizing an exposed surface of the gate and an exposed surface of the fin; and removing the fin spacer from the fin.

Abstract: A method of forming a self-forming spacer using oxidation. The self-forming spacer may include forming a fin field effect transistor on a substrate, the fin field effect transistor includes a gate on a fin, the gate is perpendicular to the fin; forming a gate spacer on the gate and a fin spacer on the fin, the gate spacer and the fin spacer are formed in a single step by oxidizing an exposed surface of the gate and an exposed surface of the fin; and removing the fin spacer from the fin.

Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

Abstract: A clamp apparatus is equipped with first and second clamp arms supported rotatably with respect to a body, and a drive unit having a pair of first and second pistons displaced under the supply of a pressure fluid. A driving force of the drive unit is transmitted to the first and second clamp arms through knuckle joints, which are connected to first and second piston rods, power-boost levers, and link arms. The power-boost levers are formed such that the length from a support pin toward the knuckle joint is longer than the length from the support pin toward the link arm.

Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

Abstract: A clamp apparatus including first and second clamp arms, which are supported rotatably on a body, with a cover being installed to cover outer sides of the body. The cover includes openings through which portions of the first and second clamp arms are inserted and rotatably operated. An unloading tray is arranged in the body at a position below the openings in the direction of gravity. Spatter, which invades into the clamp apparatus from the openings when a welding operation is carried out on a workpiece that is clamped by the first and second clamp arms, is deposited on the unloading tray, and the spatter is eliminated by taking out the unloading tray to the exterior of the clamp apparatus.

Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

Abstract: A clamping device has a pair of first and second clamping arms rotatably supported with respect to a body, and a cam member having a cam surface is removably provided at one end of each of the first and second clamping arms. A pair of rollers pivotally supported by a block body constituting a drive unit are each in contact with the cam member. By a descent of the block body under the driving action of the drive unit, the cam surface of the cam member is pressed by the rollers, and the cam surface inclined in the displacement direction of the block body and recessed in a cross-sectional arc shape is pressed.