Abstract: There is a need to ensure operations at a predetermined operating frequency when a temperature changes in an operating state. A semiconductor device includes: a bias-applied portion applied with a substrate bias; a temperature sensor to detect a temperature; and a substrate bias generator to apply the bias-applied portion with a substrate bias corresponding to the temperature detected by the temperature sensor. The bias-applied portion, while applied with a substrate bias by the substrate bias generator, shifts between an operating state and a stopped state. The substrate bias generator applies the bias-applied portion with a substrate bias configured so as not to cause an upper limit of an operating frequency for the bias-applied portion to be smaller than a predetermined value under condition of the temperature detected by the temperature sensor.

Abstract: There are included a standard deviation calculation unit that receives a plurality of acceleration data and calculates a standard deviation of the plurality of acceleration data for each specified time period, an average calculation unit that receives the plurality of acceleration data and calculates an average value of the acceleration data for each specified time period, a phase estimation unit that estimates a phase of the average value in a space having a first coordinate axis and a second coordinate axis by using the average value when the standard deviation is smaller than a specified threshold, and a phase correction unit that performs phase correction of the average value by using the estimated phase.

Abstract: An object of the invention is to transmit a waveform suitable for the reception of signals, while suppressing an increase in man-hours needed for design. A transmission-reception device (2) includes: an antenna element (21) which is terminated at a virtual ground point side of the antenna element by a terminating element (213); a conductor plane (23) which has a predetermined potential and surrounds the antenna element (21); and a transmission circuit (25) that outputs a differential signal to both ends of the antenna element (21). An interval between the conductor plane (23) and a first outer edge (214) of the antenna element (21) is shorter than an interval between the conductor plane (23) and a second outer edge (215) of the antenna element (21).

Abstract: In order to appropriately set a condition for measurement of a sensor for measuring an object to be measured in accordance with a change of an external index that can affect the object to be measured, a sensor system includes first and second sensors, a determination unit for outputting a detection signal when a measurement result of the first sensor satisfies a predetermined condition, a measurement condition storage unit for storing a condition for measurement of the second sensor, and a control unit for performing measurement by the second sensor separately from measurement in accordance with the condition for measurement, when having received the detection signal, and for updating the condition for measurement of the second sensor stored in the measurement condition storage unit based on a result of the performed measurement.

Abstract: Included are memory cells each including a resistance change element and a control circuit. The circuit performs an On writing process for applying, to the memory cell, an On writing pulse for the cell to be in a resistance state where a resistance value of the resistance change element is lower than a first reference value and an Off writing process for applying an Off writing pulse with an opposite polarity to the On writing pulse for a high resistance state with a second reference value or greater. The circuit applies, in the On writing process, a trial pulse having the same polarity as that of the On writing pulse and having the pulse width shorter than that of the On writing pulse and a reset pulse having the same polarity as that of the On writing pulse, in this order before applying the On writing pulse to the cell.

Abstract: Included are memory cells each including a resistance change element and a control circuit. The circuit performs an On writing process for applying, to the memory cell, an On writing pulse for the cell to be in a resistance state where a resistance value of the resistance change element is lower than a first reference value and an Off writing process for applying an Off writing pulse with an opposite polarity to the On writing pulse for a high resistance state with a second reference value or greater. The circuit applies, in the On writing process, a trial pulse having the same polarity as that of the On writing pulse and having the pulse width shorter than that of the On writing pulse and a reset pulse having the same polarity as that of the On writing pulse, in this order before applying the On writing pulse to the cell.

Abstract: An object of the invention is to transmit a waveform suitable for the reception of signals, while suppressing an increase in man-hours needed for design. A transmission-reception device (2) includes: an antenna element (21) which is terminated at a virtual ground point side of the antenna element by a terminating element (213); a conductor plane (23) which has a predetermined potential and surrounds the antenna element (21); and a transmission circuit (25) that outputs a differential signal to both ends of the antenna element (21). An interval between the conductor plane (23) and a first outer edge (214) of the antenna element (21) is shorter than an interval between the conductor plane (23) and a second outer edge (215) of the antenna element (21).

Abstract: There are included a standard deviation calculation unit that receives a plurality of acceleration data and calculates a standard deviation of the plurality of acceleration data for each specified time period, an average calculation unit that receives the plurality of acceleration data and calculates an average value of the acceleration data for each specified time period, a phase estimation unit that estimates a phase of the average value in a space having a first coordinate axis and a second coordinate axis by using the average value when the standard deviation is smaller than a specified threshold, and a phase correction unit that performs phase correction of the average value by using the estimated phase.

Abstract: A communication device includes a transmission equalizer that equalizes a transmission signal transmitted in a signal transmission performed via a non-contact coupling, the transmission equalizer creates a plurality of equivalent transmission signals by branching the transmission signal. The transmission equalizer includes a plurality of signal paths that respectively provide time delays different from each other to the equivalent transmission signals, and an output path that provides a filter output based on the total sum of outputs of the signal paths to the non-contact coupling, and at least one of the plurality of signal paths includes a variable delay circuit that can change a time delay to be given to the corresponding transmission signal.

Abstract: A communication device includes a transmission equalizer that equalizes a transmission signal transmitted in a signal transmission performed via a non-contact coupling, the transmission equalizer creates a plurality of equivalent transmission signals by branching the transmission signal. The transmission equalizer includes a plurality of signal paths that respectively provide time delays different from each other to the equivalent transmission signals, and an output path that provides a filter output based on the total sum of outputs of the signal paths to the non-contact coupling, and at least one of the plurality of signal paths includes a variable delay circuit that can change a time delay to be given to the corresponding transmission signal.

Abstract: In a case where a DRAM and a ReRAM are mounted together, a manufacturing cost thereof is reduced while maintaining performance of a capacitance element and a variable resistance element. A semiconductor memory device includes a variable resistance element and a capacitance element. The variable resistance element has a cylinder type MIM structure with a first depth, and is designed for a variable resistance type memory. The capacitance element has a cylinder type MIM structure with a second depth deeper than the first depth, and is designed for a DRAM.

Abstract: A transmission apparatus includes a transmission equalizer that equalizes a transmission signal transmitted in a signal transmission performed via a non-contact coupling including a magnetic coupling of a pair of coupling elements. The transmission equalizer creates plural equivalent transmission signals by branching the transmission signal; and includes plural signal paths that respectively give time delays different from each other to the equivalent transmission signals, and respectively multiplies the delayed transmission signals by tap coefficients. In addition, at least one pair of signal paths is set includes a variable delay circuit that can change the corresponding time delay to be given to the corresponding transmission signal.

Abstract: In a case where a DRAM and a ReRAM are mounted together, a manufacturing cost thereof is reduced while maintaining performance of a capacitance element and a variable resistance element. A semiconductor memory device includes a variable resistance element and a capacitance element. The variable resistance element has a cylinder type MIM structure with a first depth, and is designed for a variable resistance type memory. The capacitance element has a cylinder type MIM structure with a second depth deeper than the first depth, and is designed for a DRAM.

Abstract: A first communication device includes a first coupling element and a second communication device includes a second coupling element. The first and second communication devices are configured to wirelessly transmit, between the first and second communication devices, a differential-mode signal and a common-mode signal simultaneously through non-contact coupling between the first and second coupling elements.

Abstract: A transmission apparatus includes a transmission equalizer that equalizes a transmission signal transmitted in a signal transmission performed via a non-contact coupling including a magnetic coupling of a pair of coupling elements. The transmission equalizer creates plural equivalent transmission signals by branching the transmission signal; and includes plural signal paths that respectively give time delays different from each other to the equivalent transmission signals, and respectively multiplies the delayed transmission signals by tap coefficients. In addition, at least one pair of signal paths is set includes a variable delay circuit that can change the corresponding time delay to be given to the corresponding transmission signal.

Abstract: In a case where a DRAM and a ReRAM are mounted together, a manufacturing cost thereof is reduced while maintaining performance of a capacitance element and a variable resistance element. A semiconductor memory device includes a variable resistance element and a capacitance element. The variable resistance element has a cylinder type MIM structure with a first depth, and is designed for a variable resistance type memory. The capacitance element has a cylinder type MIM structure with a second depth deeper than the first depth, and is designed for a DRAM.

Abstract: This invention is to provide a semiconductor device having a reduced variation in the transistor characteristics. The semiconductor device has a SOI substrate, a first element isolation insulating layer, first and second conductivity type transistors, and first and second back gate contacts. The SOI substrate has a semiconductor substrate having first and second conductivity type layers, an insulating layer, and a semiconductor layer. The first element isolation insulating layer is buried in the SOI substrate, has a lower end reaching the first conductivity type layer, and isolates a first element region from a second element region. The first and second conductivity type transistors are located in the first and second element regions, respectively, and have respective channel regions formed in the semiconductor layer. The first and second back gate contacts are coupled to the second conductivity type layers in the first and second element regions, respectively.