Abstract: An object of the present invention is to provide a method of industrially producing a high-purity L-cyclic amino acid more inexpensively and with a high efficiency, from a cyclic amino acid having a double bond at the 1-position. The present invention provides a method in which an L-cyclic amino acid is produced by allowing a cyclic amino acid having a double bond at the 1-position to react with a specific enzyme having a catalytic ability to reduce a cyclic amino acid having a double bond at the 1-position to produce an L-cyclic amino acid.

Abstract: A semiconductor device includes a base, a stacked body, a plate-shaped portion, and first to third columnar portions. The stacked body is provided over the base. The plate-shaped portion is inside the stacked body from an upper end of the stacked body to the base. The first to third columnar portions are inside the stacked body from the upper end of the stacked body to the base. The second columnar portion is located away from the first columnar portion in a first direction. The third columnar portion is aligned with the first columnar portion and the second columnar portion in the first direction. A pitch between the third columnar portion and the first columnar portion is a first pitch. A pitch between the third columnar portion and the second columnar portion is a second pitch larger than the first pitch.

Abstract: A semiconductor memory device includes a substrate with a first insulating film thereon, a wiring in the first insulating film, a first electrode film on the first insulating film, a stacked body on the first electrode film, made of alternating second insulating films and second electrode films, a first insulating member extending in a direction to penetrate the stacked body, a first semiconductor film around the first insulating member and connected to the first electrode film, a third insulating film around the first semiconductor film, a first conductive member extending in the direction to penetrate the stacked body and the first electrode film, and connected to the wiring, and a fourth insulating film around the first conductive member. The fourth insulating film has the same film structure as the third insulating film.

Abstract: A semiconductor device includes a base, a stacked body, a plate-shaped portion, and first to third columnar portions. The stacked body is provided over the base. The plate-shaped portion is inside the stacked body from an upper end of the stacked body to the base. The first to third columnar portions are inside the stacked body from the upper end of the stacked body to the base. The second columnar portion is located away from the first columnar portion in a first direction. The third columnar portion is aligned with the first columnar portion and the second columnar portion in the first direction. A pitch between the third columnar portion and the first columnar portion is a first pitch. A pitch between the third columnar portion and the second columnar portion is a second pitch larger than the first pitch.

Abstract: A semiconductor memory device includes a substrate with a first insulating film thereon, a wiring in the first insulating film, a first electrode film on the first insulating film, a stacked body on the first electrode film, made of alternating second insulating films and second electrode films, a first insulating member extending in a direction to penetrate the stacked body, a first semiconductor film around the first insulating member and connected to the first electrode film, a third insulating film around the first semiconductor film, a first conductive member extending in the direction to penetrate the stacked body and the first electrode film, and connected to the wiring, and a fourth insulating film around the first conductive member. The fourth insulating film has the same film structure as the third insulating film.

Abstract: The performance of a semiconductor device having a memory element is improved. An insulating film, which is a gate insulating film for a memory element, is formed on a semiconductor substrate, and a gate electrode for the memory element is formed on the insulating film. The insulating film has a first insulating film, a second insulating film thereon, and a third insulating film thereon. The second insulating film is a high-dielectric constant insulator film having a charge accumulating function and contains hafnium, silicon, and oxygen. Each of the first insulating film and the third insulating film has a band gap larger than the band gap of the second insulating film.

Abstract: The performance of a semiconductor device having a memory element is improved. An insulating film, which is a gate insulating film for a memory element, is formed on a semiconductor substrate, and a gate electrode for the memory element is formed on the insulating film. The insulating film has a first insulating film, a second insulating film thereon, and a third insulating film thereon. The second insulating film is a high-dielectric constant insulator film having a charge accumulating function and contains hafnium, silicon, and oxygen. Each of the first insulating film and the third insulating film has a band gap larger than the band gap of the second insulating film.

Abstract: Disclosed is a semiconductor device including a first MISFET of an n channel type and a second MISFET of a p channel type, each of the MISFETs being configured with a gate insulating film featuring a silicon oxide film or a silicon oxynitride film and a gate electrode including a conductive silicon film positioned on the gate insulating film. Metal elements such as Hf are introduced near the interface between the gate electrode and the gate insulating film in both the first and second MISFETs such that metal atoms with a surface density of 1×1013 to 5×1014 atoms/cm2 are contained near the interface and each of the first and second MISFETs having a channel region containing an impurity the concentration of which is equal to or lower than 1.2×1018/cm3.

Abstract: Disclosed is a semiconductor device including a first MISFET of an n channel type and a second MISFET of a p channel type, each of the MISFETs being configured with a gate insulating film featuring a silicon oxide film or a silicon oxynitride film and a gate electrode including a conductive silicon film positioned on the gate insulating film. Metal elements such as Hf are introduced near the interface between the gate electrode and the gate insulating film in both the first and second MISFETs such that metal atoms with a surface density of 1×1013 to 5×1014 atoms/cm2 are contained near the interface and each of the first and second MISFETs having a channel region containing an impurity the concentration of which is equal to or lower than 1.2×1018/cm3.

Abstract: Manufacturing technique for a semiconductor device having a first MISFET of an n channel-type and a second MISFET of a p channel type, including forming a first insulating film composed of a silicon oxide film or a silicon oxynitride film on a semiconductor substrate for forming a gate insulating film of the respective MISFETs; depositing metal elements on the first insulating film; forming of a silicon film on the first insulating film for the forming of a gate electrode of the respective MISFETs; and producing the respective gate electrodes by patterning the silicon film. The depositing of the metal films on the first insulating film is such that there is produced in the vicinity of the interface between the gate electrode and the gate insulating film a surface density of the metal elements within a range of 1×1013 to 5×1014 atoms/cm2.

Abstract: There is provided a technology capable of achieving, in a semiconductor device having a MISFET using an insulating film containing hafnium as a gate insulating film, an improvement in the reliability of a MISFET. In the present invention, the gate insulating film of an n-channel core transistor is provided with a structure different from that of the gate insulating film of a p-channel core transistor. Specifically, in the n-channel core transistor, as the gate insulating film thereof, a laminate film of a silicon oxide film and a HfZrSiON film is used. On the other hand, in the p-channel core transistor, as the gate insulating film thereof, a laminate film of a silicon oxide film and a HfSiON film is used.

Abstract: Manufacturing technique for a semiconductor device having a first MISFET of an n channel-type and a second MISFET of a p channel type, including forming a first insulating film composed of a silicon oxide film or a silicon oxynitride film on a semiconductor substrate for forming a gate insulating film of the respective MISFETs; depositing metal elements on the first insulating film; forming of a silicon film on the first insulating film for the forming of a gate electrode of the respective MISFETs; and producing the respective gate electrodes by patterning the silicon film. The depositing of the metal films on the first insulating film is such that there is produced in the vicinity of the interface between the gate electrode and the gate insulating film a surface density of the metal elements within a range of 1×1013 to 5×1014 atoms/cm2.

Abstract: An object of the present invention is to improve the performance of a semiconductor device having a CMISFET. Each of an n channel MISFET and a p channel MISFET which form the CMISFET includes a gate insulating film composed of a silicon oxynitride film and a gate electrode including a silicon film positioned on the gate insulating film. Metal elements such as Hf are introduced near the interface between the gate electrode and the gate insulating film with a surface density of 1×1013 to 5×1014 atoms/cm2. The impurity concentration of channel regions of the n channel MISFET and the p channel MISFET is controlled to be equal to or lower than 1.2×1018/cm3.

Abstract: The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.

Abstract: The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.

Abstract: The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.

Abstract: The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.

Abstract: An object of the present invention is to improve the performance of a semiconductor device having a CMISFET. Each of an n channel MISFET and a p channel MISFET which form the CMISFET includes a gate insulating film composed of a silicon oxynitride film and a gate electrode including a silicon film positioned on the gate insulating film. Metal elements such as Hf are introduced near the interface between the gate electrode and the gate insulating film with a surface density of 1×1013 to 5×1014 atoms/cm2. The impurity concentration of channel regions of the n channel MISFET and the p channel MISFET is controlled to be equal to or lower than 1.2×1018/cm3.

Abstract: A MISFET includes: a p type substrate having a channel region with an impurity concentration C; an insulating film made of SiO2 and formed on the channel region; and an insulating film made of HfSiON and formed on the gate insulating film. When there is a postulated MISFET including a postulated substrate having a channel region with the impurity concentration C and made of a material identical to the substrate and an insulating film made solely of SiON formed on the channel region, said impurity concentration C of channel region is set so that a maximum value of mobility of electrons in said channel region is higher than a maximum value of mobility of electrons in the postulated channel region. Thus, the power supply voltage can be reduced and the power consumption can be reduced.

Abstract: A &bgr;-primeverosidase gene characterized by encoding a protein containing the amino acid sequence represented by SEQ ID NO:1 in the Sequence Listing or an amino acid sequence derived from this sequence by deletion, substitution, insertion or addition of one or more amino acids and utilization thereof.