Patents by Inventor Masaharu Ninomiya
Masaharu Ninomiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8110486Abstract: A semiconductor wafer is produced at a step of forming a lattice relaxation or a partly lattice-relaxed strain relaxation SiGe layer on an insulating layer in a SOI wafer comprising an insulating layer and a SOI layer, wherein at least an upper layer side portion of the SiGe layer is formed on the SOI layer at a gradient of Ge concentration gradually decreasing toward the surface and then subjected to a heat treatment in an oxidizing atmosphere.Type: GrantFiled: January 5, 2007Date of Patent: February 7, 2012Assignee: Sumco CorporationInventors: Koji Matsumoto, Tomoyuki Hora, Akihiko Endo, Etsurou Morita, Masaharu Ninomiya
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Patent number: 7977221Abstract: A strained Si—SOI substrate, and a method for producing the same are provided, wherein the method includes the steps of growing a SiGe mixed crystal layer 14 on an SOI substrate 10 having an Si layer 13 and a buried oxide film 12; forming protective films 15, 16 on the surface of the SiGe mixed crystal layer 14; implanting light element ions into a vicinity of the interface between the Si layer 13 and the buried oxide film 12; performing a first heat treatment at a temperature in the range of 400 to 1000° C.; performing a second heat treatment at a temperature not lower than 1050° C. under an oxidizing atmosphere; performing a third heat treatment at a temperature not lower than 1050° C. under an inert atmosphere; removing the Si oxide film 18 formed on the surface; and forming a strained Si layer 19.Type: GrantFiled: October 5, 2007Date of Patent: July 12, 2011Assignees: Sumco Corporation, Kyushu University, National University CorporationInventors: Masaharu Ninomiya, Koji Matsumoto, Masahiko Nakamae, Masanobu Miyao
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Publication number: 20110025838Abstract: An object of the present invention is to simplify the defect inspection of an internal defect and front and rear surface defects in a wafer.Type: ApplicationFiled: July 20, 2010Publication date: February 3, 2011Applicant: SUMCO CORPORATIONInventor: Masaharu NINOMIYA
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Patent number: 7767548Abstract: A method for manufacturing a semiconductor wafer with a strained Si layer having sufficient tensile strain and few crystal defects, while achieving a relatively simple layered structure, is provided.Type: GrantFiled: August 17, 2007Date of Patent: August 3, 2010Assignees: Sumco Corporation, Kyushu University, National University CorporationInventors: Masaharu Ninomiya, Koji Matsumoto, Masahiko Nakamae, Masanobu Miyao, Taizoh Sadoh
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Publication number: 20090090933Abstract: A strained Si-SOI substrate, and a method for producing the same are provided, wherein the method includes the steps of growing a SiGe mixed crystal layer 14 on an SOI substrate 10 having an Si layer 13 and a buried oxide film 12; forming protective films 15, 16 on the surface of the SiGe mixed crystal layer 14; implanting light element ions into a vicinity of the interface between the Si layer 13 and the buried oxide film 12; performing a first heat treatment at a temperature in the range of 400 to 1000° C.; performing a second heat treatment at a temperature not lower than 1050° C. under an oxidizing atmosphere; performing a third heat treatment at a temperature not lower than 1050° C. under an inert atmosphere; removing the Si oxide film 18 formed on the surface; and forming a strained Si layer 19.Type: ApplicationFiled: October 5, 2007Publication date: April 9, 2009Applicants: Sumco Corporation, Kyushu University, National University CorporationInventors: Masaharu Ninomiya, Koji Matsumoto, Masahiko Nakamae, Masanobu Miyao
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Publication number: 20090047526Abstract: A method for manufacturing a semiconductor wafer with a strained Si layer having sufficient tensile strain and few crystal defects, while achieving a relatively simple layered structure, is provided.Type: ApplicationFiled: August 17, 2007Publication date: February 19, 2009Inventors: Masaharu Ninomiya, Koji Matsumoto, Masahiko Nakamae, Masanobu Miyao, Taizoh Sadoh
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Patent number: 7405142Abstract: A semiconductor substrate manufacturing method has a first layer formation process, a second layer formation process, a heat treatment process, and a polishing process; in the first layer formation process, the thickness of the first SiGe layer is set to less than twice the critical thickness, which is the film thickness at which dislocations appear and lattice relaxation occurs due to increasing film thickness; in the second layer formation process, the Ge composition ratio of the second SiGe layer is at least at the contact face with the first SiGe layer or with the Si layer, set lower than the maximum value of the Ge composition ratio in the first SiGe layer, and moreover, a gradient composition region in at least a portion of which the Ge composition ratio increases gradually toward the surface is formed.Type: GrantFiled: February 6, 2003Date of Patent: July 29, 2008Assignee: Sumco CorporationInventors: Ichiro Shiono, Masaharu Ninomiya, Hazumu Kougami
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Publication number: 20070166929Abstract: A semiconductor wafer is produced at a step of forming a lattice relaxation or a partly lattice-relaxed strain relaxation SiGe layer on an insulating layer in a SOI wafer comprising an insulating layer and a SOI layer, wherein at least an upper layer side portion of the SiGe layer is formed on the SOI layer at a gradient of Ge concentration gradually decreasing toward the surface and then subjected to a heat treatment in an oxidizing atmosphere.Type: ApplicationFiled: January 5, 2007Publication date: July 19, 2007Applicant: SUMCO CORPORATIONInventors: Koji Matsumoto, Tomoyuki Hora, Akihiko Endo, Etsurou Morita, Masaharu Ninomiya
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Patent number: 7198997Abstract: In a semiconductor substrate, a field effect transistor, and methods for producing the same, in order to lower threading dislocation density and also to lower surface roughness, a step of repeating, a plurality of times, a process of epitaxially growing a SiGe gradient composition layer of which a Ge composition ratio is gradually increased from a Ge composition ratio of a base material and a process of epitaxially growing a SiGe constant-composition layer on the gradient composition layer at a final Ge composition ratio of the gradient composition layer, thereby depositing a SiGe layer of which a Ge composition ratio changes in a film deposition direction, in a step-like manner with a gradient, a heat treatment step of performing heat treatment at a temperature exceeding a temperature of the epitaxial growth either during or after formation of the SiGe layer, and a polishing step of polishing to remove irregularities on a surface of the SiGe layer which arise in the heat treatment after formation of the SiGeType: GrantFiled: November 29, 2002Date of Patent: April 3, 2007Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Ichiro Shiono, Masaharu Ninomiya, Hazumu Kougami
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Publication number: 20060258126Abstract: A semiconductor substrate manufacturing method has a first layer formation process, a second layer formation process, a heat treatment process, and a polishing process; in the first layer formation process, the thickness of the first SiGe layer is set to less than twice the critical thickness, which is the film thickness at which dislocations appear and lattice relaxation occurs due to increasing film thickness; in the second layer formation process, the Ge composition ratio of the second SiGe layer is at least at the contact face with the first SiGe layer or with the Si layer, set lower than the maximum value of the Ge composition ratio in the first SiGe layer, and moreover, a gradient composition region in at least a portion of which the Ge composition ratio increases gradually toward the surface is formed.Type: ApplicationFiled: February 6, 2003Publication date: November 16, 2006Applicant: SUMCO CORPORATIONInventors: Ichiro Shiono, Masaharu Ninomiya, Hazumu Kougami
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Publication number: 20060214257Abstract: A strained Si-SOI substrate is produced by a method comprising: growing a SiGe mixed crystal layer on an SOI substrate having a Si layer of not less than 5 nm in thickness and a buried oxide layer; forming a protective film on the SiGe mixed crystal layer; implanting light element ions into a vicinity of an interface between the silicon layer and the buried oxide layer; a first heat treatment for heat treating the substrate at a temperature of 400 to 1000° C. in an inert gas atmosphere; a second heat treatment for heat treating the substrate at a temperature not lower than 1050° C. in an oxidizing atmosphere containing chlorine; removing an oxide film from the surface of the substrate, and forming a strained silicon layer on the surface of the substrate.Type: ApplicationFiled: March 23, 2006Publication date: September 28, 2006Inventors: Masaharu Ninomiya, Koji Matsumoto, Masahiko Nakamae, Masanobu Miyao
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Publication number: 20060022200Abstract: In a semiconductor substrate, a field effect transistor, and methods for producing the same, in order to lower threading dislocation density and also to lower surface roughness, a step of repeating, a plurality of times, a process of epitaxially growing a SiGe gradient composition layer of which a Ge composition ratio is gradually increased from a Ge composition ratio of a base material and a process of epitaxially growing a SiGe constant-composition layer on the gradient composition layer at a final Ge composition ratio of the gradient composition layer, thereby depositing a SiGe layer of which a Ge composition ratio changes in a film deposition direction, in a step-like manner with a gradient, a heat treatment step of performing heat treatment at a temperature exceeding a temperature of the epitaxial growth either during or after formation of the SiGe layer, and a polishing step of polishing to remove irregularities on a surface of the SiGe layer which arise in the heat treatment after formation of the SiGeType: ApplicationFiled: November 29, 2002Publication date: February 2, 2006Applicant: Sumitomo Mitsubishi Silicon CorporationInventors: Ichiro Shiono, Masaharu Ninomiya, Hazumu Kougami
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Patent number: 6277193Abstract: A method for manufacturing semiconductor silicon epitaxial wafer and semiconductor device by which a gettering ability can be given to an epitaxial wafer in which the formation of BMD is not able to be expected in both low- and high-temperature device manufacturing processes, with the manufacturing processes being lower and higher than 1,050° C. in temperature, and has a specific resistance of ≧10 m&OHgr;·cm. When this method is used, such BMD that is sufficient to obtain gettering can be formed in both the low- and high-temperature processes, with the manufacturing processes being lower and higher than 1,050° C. in temperature, even in the epitaxial wafer having a specific resistance of ≧10 m&OHgr;·cm by performing low-temperature heat treatment at 650˜900° C.Type: GrantFiled: June 2, 1999Date of Patent: August 21, 2001Assignee: Sumitomo Metal Industries, Ltd.Inventors: Shinsuke Sadamitsu, Tooru Nagashima, Yasuo Koike, Masaharu Ninomiya, Takeshi Kii
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Patent number: 6261362Abstract: The objective of this invention is to provide a manufacturing method wherewith optimally low-COP substrates can be efficiently manufactured for epitaxial wafers in order to obtain high epitaxial surface quality that will not have an adverse effect on device characteristics. A phenomenon was discovered whereby COPs are eliminated by solution annealing or flattening when epitaxial films are formed on wafers wherein the density of grown-in defects (COPs) with a size of 0.130 &mgr;m or larger is 0.03 defects/cm2 or lower, the use of which phenomenon is characteristic of the invention.Type: GrantFiled: September 14, 1999Date of Patent: July 17, 2001Assignee: Sumitomo Metal Industries, Ltd.Inventors: Takashi Fujikawa, Masaharu Ninomiya