Abstract: An information record/reproduction apparatus includes logical volumes that can be used as a variable-length record/reproduction area and a physical volume that has been divided into a plurality of fixed-length areas and is not subjected to record or reproduction. Allocation to the logical volume is made by combining the divided fixed-length physical volumes by a management unit, and the size of the information storage area can be set depending upon, for example, a category of information to be recorded. If the amount of information of high priority exceeds a size of a predetermined logical volume corresponding to the information while no unused physical volume is available, then the management unit detaches part of a logical volume in which information of low priority has been recorded, allocates the detached part to the logical volume corresponding to the information, and thus records the exceeding amount of information.

Abstract: An information record/reproduction apparatus includes logical volumes that can be used as a variable-length record/reproduction area and a physical volume that has been divided into a plurality of fixed-length areas and is not subjected to record or reproduction. Allocation to the logical volume is made by combining the divided fixed-length physical volumes by a management unit, and the size of the information storage area can be set depending upon, for example, a category of information to be recorded. If the amount of information of high priority exceeds a size of a predetermined logical volume corresponding to the information while no unused physical volume is available, then the management unit detaches part of a logical volume in which information of low priority has been recorded, allocates the detached part to the logical volume corresponding to the information, and thus records the exceeding amount of information.

Abstract: The invention eliminates a race condition without restricting reception speed. The invention provides a method of designing a serial-to-parallel conversion circuit, the method including determining a rule for data and a strobe when a first-stage memory device in a shift register latches data and when the memory device holds the data; providing a logical circuit for generating an output conforming to the rule at a data input side of the shift register; and shifting a data latch timing of the memory device by a half-period.

Abstract: The invention eliminates a race condition without restricting reception speed. The invention provides a method of designing a serial-to-parallel conversion circuit, the method including determining a rule for data and a strobe when a first-stage memory device in a shift register latches data and when the memory device holds the data; providing a logical circuit for generating an output conforming to the rule at a data input side of the shift register; and shifting a data latch timing of the memory device by a half-period.