Patents by Inventor Masaharu Terauchi

Masaharu Terauchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050218805
    Abstract: A plasma display panel in which a plurality of pairs of first and second electrodes are disposed on a first substrate so as to be parallel to each other, a plurality of third electrodes are disposed on a second substrate, and main parts of a plurality of barrier ribs are disposed between adjacent third electrodes, the third electrodes being orthogonal to a longitudinal direction of display electrodes each of which consists of a pair of the first and second electrodes, wherein a plurality of fourth electrodes are fixed to the barrier ribs or areas of a surface of the first substrate facing the barrier ribs so as to be at least in vicinities of areas between adjacent display electrodes, the fourth electrodes being electrically exposed to discharge spaces which are defined by the barrier ribs.
    Type: Application
    Filed: November 28, 2003
    Publication date: October 6, 2005
    Inventors: Masatoshi Kitagawa, Masaharu Terauchi, Yukihiro Morta, Shinichiro Hashimoto
  • Publication number: 20050104532
    Abstract: A method for restoring the function of a plasma display panel according to the present invention restores a function of a plasma display panel by raising the temperature of the plasma display panel to 400° C. to 800° C.
    Type: Application
    Filed: November 18, 2004
    Publication date: May 19, 2005
    Inventors: Tomohiro Okumura, Mitsuo Saitoh, Masashi Morita, Masaharu Terauchi, Junko Asayama
  • Publication number: 20050040765
    Abstract: A fluorine-containing precoating (not shown) is formed to cover a phosphor particle (7) by, for example, a physical vapor deposition of a fluoride. Then, a fluorine-containing coating (8) covering the phosphor particle (7) is formed by supplying fluorine into the precoating. Thus obtained phosphor particle (7) with the coating (8) is applied in the form of a paste to a substrate (1) on each electrode (2) is between adjacent two ribs (4) to form a phosphor layer (6) including the phosphor particles (7) between the ribs (4) on the substrate (1). The substrate (1) is positioned with respect to another substrate (not shown) having electrodes thereon to form discharge spaces between the substrates. The discharge spade is filled with a discharge gas to produce a plasma display panel (PDP).
    Type: Application
    Filed: August 18, 2004
    Publication date: February 24, 2005
    Inventors: Tomohiro Okumura, Mitsuo Saitoh, Masashi Morita, Takafumi Okuma, Masaharu Terauchi, Junko Asayama
  • Publication number: 20050017218
    Abstract: Phosphors having high luminescence characteristics are provided while achieving manufacturing cost reductions by minimizing the usage amount of Eu, the luminescence center. Also provided are a display device (PDP, etc) and a fluorescent lamp having excellent display and/or luminescence characteristics as a result of using the phosphors, while achieving manufacturing cost reductions by minimizing the Eu usage amount.
    Type: Application
    Filed: June 14, 2004
    Publication date: January 27, 2005
    Inventors: Takehiro Zukawa, Masatoshi Kitagawa, Masaharu Terauchi, Junko Asayama, Masahiro Sakai
  • Patent number: 6846728
    Abstract: By applying ion or optical energy or catalytic effects at the time of depositing a crystalline silicon thin film, improvements in crystallinity of the crystalline silicon thin film in proximities of an interface of a substrate or smoothing of its surface may be achieved. With this arrangement, it is possible to achieve improvements in crystallinity of the crystalline silicon film that is formed in a low temperature condition through CVD method and to prevent concaves and convexes from being formed on its surface or to prevent oxidation of grain fields, and it is accordingly possible to provide a thin film transistor, a semiconductor device such as a solar cell and methods for manufacturing these that exhibit superior characteristics and reliability.
    Type: Grant
    Filed: March 6, 2003
    Date of Patent: January 25, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masashi Goto, Mikihiko Nishitani, Masaharu Terauchi
  • Publication number: 20040145314
    Abstract: A light emitting device that emits visible light caused by ultraviolet rays from a discharge generated in a discharge medium including a rare gas, wherein a phosphorous material is disposed in a vessel that is hermetically sealed and contains the discharge medium, and a photocatalyst is disposed at one or more positions inside the vessel, the positions being reachable for one or both of the ultraviolet rays and light emitted from the phosphorous material, so that the photocatalyst is in contact with the discharge medium.
    Type: Application
    Filed: November 13, 2003
    Publication date: July 29, 2004
    Inventors: Takehiro Zukawa, Masatoshi Kitagawa, Masaharu Terauchi, Junko Asayama
  • Publication number: 20040145316
    Abstract: A plasma display panel is composed of a first substrate and a second substrate facing each other via a discharge space and sealed together. A protective layer on the first substrate is composed principally of magnesium oxide, includes a substance or structure that creates a first energy level in an area of a forbidden band, the area being in a vicinity of a conduction band, and includes a substance or structure that creates a second energy level in another area in the forbidden band, the other area being in a vicinity of a valence band. During driving the second energy level is occupied by electrons, and few electrons exist in the first energy level, or electrons can easily occupy the first energy level due to a minus charge state, and MgO insultaive resistance is not lowered. This maintains wall charge retention and reduces discharge irregularities and firing voltage Vf.
    Type: Application
    Filed: November 6, 2003
    Publication date: July 29, 2004
    Inventors: Mikihiko Nishitani, Yukihiro Morita, Masatoshi Kitagawa, Masaharu Terauchi
  • Publication number: 20030162373
    Abstract: By applying ion or optical energy or catalytic effects at the time of depositing a crystalline silicon thin film, improvements in crystallinity of the crystalline silicon thin film in proximities of an interface of a substrate or smoothing of its surface may be achieved. With this arrangement, it is possible to achieve improvements in crystallinity of the crystalline silicon film that is formed in a low temperature condition through CVD method and to prevent concaves and convexes from being formed on its surface or to prevent oxidation of grain fields, and it is accordingly possible to provide a thin film transistor, a semiconductor device such as a solar cell and methods for manufacturing these that exhibit superior characteristics and reliability.
    Type: Application
    Filed: March 6, 2003
    Publication date: August 28, 2003
    Applicant: Matsushita Elec. Ind. Co. Ltd.
    Inventors: Masashi Goto, Mikihiko Nishitani, Masaharu Terauchi
  • Publication number: 20030143787
    Abstract: In the production of channel etch type bottom gate thin film transistors, etching damage in a channel etch step is prevented to improve the transistor performance. The channel etch is performed using non-ionic excited species, such as hydrogen radicals and fluorine radicals, generated by contact-decomposition reaction which utilizes a metal heated by electric resistance heating. Alternatively, in place of the channel etch, a portion of the source/drain semiconductor thin film immediately above the channel is nitrided by a non-ionic nitrogen-containing decomposition product that is produced by contacting molecules of a chemical substance containing nitrogen atoms with a metal heated by electric resistance heating to decompose the chemical molecules.
    Type: Application
    Filed: January 9, 2003
    Publication date: July 31, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahiro Sakai, Masaharu Terauchi
  • Patent number: 6548380
    Abstract: By applying ion or optical energy or catalytic effects at the time of depositing a crystalline silicon thin film, improvements in crystallinity of the crystalline silicon thin film in proximities of an interface of a substrate or smoothing of its surface may be achieved. With this arrangement, it is possible to achieve improvements in crystallinity of the crystalline silicon film that is formed in a low temperature condition through CVD method and to prevent concaves and convexes from being formed on its surface or to prevent oxidation of grain fields, and it is accordingly possible to provide a thin film transistor, a semiconductor device such as a solar cell and methods for manufacturing these that exhibit superior characteristics and reliability.
    Type: Grant
    Filed: September 8, 2000
    Date of Patent: April 15, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masashi Goto, Mikihiko Nishitani, Masaharu Terauchi
  • Patent number: 6524958
    Abstract: In the production of channel etch type bottom gate thin film transistors, etching damage in a channel etch step is prevented to improve the transistor performance. The channel etch is performed using non-ionic excited species, such as hydrogen radicals and fluorine radicals, generated by contact-decomposition reaction which utilizes a metal heated by electric resistance heating. Alternatively, in place of the channel etch, a portion of the source/drain semiconductor thin film immediately above the channel is nitrided by a non-ionic nitrogen-containing decomposition product that is produced by contacting molecules of a chemical substance containing nitrogen atoms with a metal heated by electric resistance heating to decompose the chemical molecules.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: February 25, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahiro Sakai, Masaharu Terauchi
  • Publication number: 20020055211
    Abstract: In the production of channel etch type bottom gate thin film transistors, etching damage in a channel etch step is prevented to improve the transistor performance. The channel etch is performed using non-ionic excited species, such as hydrogen radicals and fluorine radicals, generated by contact-decomposition reaction which utilizes a metal heated by electric resistance heating. Alternatively, in place of the channel etch, a portion of the source/drain semiconductor thin film immediately above the channel is nitrided by a non-ionic nitrogen-containing decomposition product that is produced by contacting molecules of a chemical substance containing nitrogen atoms with a metal heated by electric resistance heating to decompose the chemical molecules.
    Type: Application
    Filed: November 8, 2001
    Publication date: May 9, 2002
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Masahiro Sakai, Masaharu Terauchi
  • Patent number: 5728231
    Abstract: A precursor for manufacturing a semiconductor thin film in which an oxide thin film comprising at least one element as a dopant, selected from a group which consists of Groups IA, IIA, IIB, VA, and VB elements, and Groups IB and IIIA elements which are main components of the semiconductor thin film are deposited on a substrate, or a precursor for manufacturing a semiconductor thin film which is formed by depositing a thin film of oxide comprising the Groups IB and IIIA elements on the substrate wherein the content of at least one of the Groups IB and IIIA elements is varied in the direction of film thickness, and a method for manufacturing a semiconductor thin film comprising the step of heat treating the precursor for manufacturing the semiconductor thin film in an atmosphere containing a Group VIA element.
    Type: Grant
    Filed: May 15, 1996
    Date of Patent: March 17, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takayuki Negami, Masaharu Terauchi, Mikihiko Nishitani, Takahiro Wada
  • Patent number: 5500056
    Abstract: A solar cell includes a compound semiconductor, which is a laminated film having compound semiconductor layers, and low melting point glass. When the solar cell is heated by fire, the low melting point glass melts to seal the compound semiconductor so that toxic substances contained in the compound semiconductor are not released into the air.
    Type: Grant
    Filed: July 18, 1994
    Date of Patent: March 19, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takahiro Wada, Mitsusuke Ikeda, Mikihiko Nishitani, Masaharu Terauchi, Takayuki Negami, Naoki Kohara