Patents by Inventor Masaharu Udagawa

Masaharu Udagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5486706
    Abstract: By etching, a first groove and a second groove are formed in a silicon substrate. Surfaces of the side walls of these grooves have a surface orientation of (111). The first and second grooves sandwich a silicon thin plate therebetween, which is formed as a part of the silicon substrate. The silicon thin plate is sufficiently thin so as to act as a quantum well. Further, a pair of silicon oxide films acting as tunneling barriers are formed on the surfaces of the side walls of the silicon thin plate, thus forming a double barrier structure. In addition, a pair of polysilicon electrodes are formed and sandwich the double barrier structure. As a result, the structure of a resonance tunneling diode, which utilizes the resonance tunneling effect, is provided. Adding a third electrode to the above structure provides a hot electron transistor.
    Type: Grant
    Filed: May 26, 1994
    Date of Patent: January 23, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichiro Yuki, Yoshihiko Hirai, Kiyoshi Morimoto, Masaaki Niwa, Juro Yasui, Kenji Okada, Masaharu Udagawa
  • Patent number: 5480492
    Abstract: For removing an unnecessary substance on a silicon substrate surface, a temperature of the unnecessary substance on the silicon substrate surface is not less than 750.degree. C. when the unnecessary substance is exposed to a gas including ozone.
    Type: Grant
    Filed: October 15, 1993
    Date of Patent: January 2, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaharu Udagawa, Juro Yasui, Masaaki Niwa, Yoshihiko Hirai, Kenji Okada, Kiyoshi Morimoto, Koichiro Yuki
  • Patent number: 5444267
    Abstract: A quantum device including a plate-like conductor part having a necking portion made by forming a first mask layer having a first strip portion on a conductor substrate; forming a second mask layer having a second strip portion on the conductor substrate; etching a region of the conductor substrate which is not covered with the first and second mask layers, by using the first and second mask layers as an etching mask, to form a plurality of first recess portions on a surface of the conductor substrate; selectively covering side faces of the plurality of first recess portions, and side faces of the first and second mask layers with a side wall film; selectively removing only the second mask layer; etching another region of the conductor substrate which is not covered with the first mask layer and the side wall film, by using the first mask layer and the side wall film as an etching mask, to form a plurality of second recess portions on the surface of the conductor substrate; selectively removing part of anothe
    Type: Grant
    Filed: October 28, 1994
    Date of Patent: August 22, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenji Okada, Kiyoshi Morimoto, Masaharu Udagawa, Koichiro Yuki, Masaaki Niwa, Yoshihiko Hirai, Juro Yasui
  • Patent number: 5422306
    Abstract: A method is disclosed of forming semiconductor hetero interfaces that will contribute to the performance improvement of devices having semiconductor hetero interfaces such as MOS transistors, quantum devices, capacitors and the like. The method comprises the steps of making the surface of a semiconductor substrate clean and flat in terms of atomic level by heating said semiconductor substrate in vacuum to a temperature at which reconstruction of the surface atoms of said semiconductor substrate takes place, then forming a structural buffer layer such as a native oxide layer and the like on said semiconductor substrate surface after the temperature of said semiconductor substrate was lowered to room temperature and finally subjecting the semiconductor substrate with said structural buffer layer formed on its surface to a thermal treatment performed in certain specified temperature and atmosphere.
    Type: Grant
    Filed: December 15, 1992
    Date of Patent: June 6, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaaki Niwa, Masaharu Udagawa, Yoshihiko Hirai, Juurou Yasui
  • Patent number: 5405454
    Abstract: A silicon substrate comprises, at least two surfaces extending substantially along respective crystal faces of (111) crystal orientation of the silicon, the crystal faces of (111) crystal orientation crossing with each other, an electrically insulating layer formed by oxidizing the silicon substrate from the surfaces, and an electrically conductive portion insulated electrically by the electrically insulating layer from an outside of the silicon substrate.
    Type: Grant
    Filed: March 12, 1993
    Date of Patent: April 11, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihiko Hirai, Kiyoshi Morimoto, Yasuaki Terui, Masaaki Niwa, Juro Yasui, Kenji Okada, Masaharu Udagawa, Koichiro Yuki