Abstract: A multiprocessor having a plurality of processor elements connected in a cascaded manner. A memory is shared between each processor element and a processor adjacent in an upper or lower rank to the processor. In the lower processor element, there are disposed an arbiter for arbitrating a memory access with its upper processor element and a bus selector for switching a bus with the arbiter. The processor elements are connected in a multistage tree structure by a bus connection only. From the upper processor element, therefore, there can be accessed the shared memory in the lower processor element only through an external bus. The whole system is not limited by the address space of each processor and the bus, even if the address space is finite, so that the real memory capacity can be limitlessly expanded in a manner to correspond to the internal memory of each processor element.

Abstract: A bus control method and apparatus wherein buses each coupling a pair of processors are serially arranged rectilinearly into a cluster bus which is arranged in one direction and wherein a plurality of such cluster buses are arranged in a plurality of directions as a lattice pattern to form a multiprocessor system. Each of the processors supplies the respective cluster buses with send request and priority processing level signals and receives a receipt acknowledge signal from another processor on the same cluster bus, thereby to occupy said cluster bus, so as to transfer data to the other processor on the cluster bus.