Patents by Inventor Masaharu Yasuda
Masaharu Yasuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230232540Abstract: In manufacturing a printed circuit board using a semi-additive method, a removal liquid that has been used in removing a nickel-chromium-containing layer (5) is regenerated by contacting the removal liquid with a chelate resin having a functional group represented by a following formula (1) : where a plurality of Rs are identical divalent hydrocarbon groups having 1 to 5 carbons, and a portion of hydrogen atoms may be substituted with halogen atoms.Type: ApplicationFiled: November 16, 2021Publication date: July 20, 2023Inventors: Shoichiro SAKAI, Ryuta OHSUKA, Koji NITTA, Yoshihito YAMAGUCHI, Masaharu YASUDA, Akira TSUCHIKO, Koji KASUYA, Kenji NISHIE, Yu FUKUI
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Publication number: 20230212757Abstract: A regenerating method of a removal liquid including: removing a nickel-chromium-containing layer from a substrate using the removal liquid at a time of manufacturing a printed circuit board by a semi-additive method, the substrate including the nickel-chromium-containing layer and a copper-containing layer; collecting the removal liquid that has been used; and contacting the collected removal liquid in collecting the removal liquid with a chelate resin, wherein the chelate resin includes a functional group represented by a following formula (1): where a plurality of Rs are identical divalent hydrocarbon groups having 1 to 5 carbons, and a portion of hydrogen atoms in the hydrocarbon groups are substituted with halogen atoms or not substituted with a halogen atom.Type: ApplicationFiled: November 16, 2021Publication date: July 6, 2023Inventors: Ryuta OHSUKA, Koji NITTA, Shoichiro SAKAI, Yoshihito YAMAGUCHI, Masaharu YASUDA, Akira TSUCHIKO, Koji KASUYA, Kenji NISHIE, Yu FUKUI
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Publication number: 20160381793Abstract: A wiring board of the present disclosure includes an insulating layer and a wiring conductor. The wiring conductor is buried in an insulating layer in such a manner as to have a top surface exposed to a surface of the insulating layer. The wiring conductor includes, at a portion buried in the insulating layer, a wiring level difference part or a wiring inclined part having a width larger than a width of the top surface.Type: ApplicationFiled: June 22, 2016Publication date: December 29, 2016Applicant: KYOCERA CorporationInventors: Masaharu YASUDA, Yoshihiro HASEGAWA
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Patent number: 9502340Abstract: A method for manufacturing a wiring board according to the present invention includes the steps of preparing a supporting substrate having a product forming region and a marginal region; preparing a separable metal foil whose area is larger than that of the product forming region and is smaller than that of the supporting substrate; fixing the separable metal foil to the supporting substrate by burying into the supporting substrate; forming a build-up section on the buried separable metal foil; integrally cutting out the supporting substrate, the separable metal foil and the build-up section; obtaining a laminated body for wiring board composed of the second metal foil and the build-up section by separating the first metal foil and the second metal foil; and forming the wiring conductor layer by removing a part of the second metal foil.Type: GrantFiled: December 10, 2013Date of Patent: November 22, 2016Assignee: KYOCERA CORPORATIONInventors: Daisuke Narumi, Yoshinori Nakatomi, Masaharu Yasuda
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Publication number: 20160219698Abstract: A wiring board of the present invention includes a build-up layer having a plurality of insulating layers laminated one upon another, a groove formed on a major surface of each of the insulating layers, and a wiring conductor formed in the groove. A surface of the wiring conductor lies lower than the major surface of each of the insulating layers which is formed in the wiring conductor in the groove.Type: ApplicationFiled: January 20, 2016Publication date: July 28, 2016Applicant: KYOCERA Circuit Solutions, Inc.Inventor: Masaharu YASUDA
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Publication number: 20150195922Abstract: A method for manufacturing a wiring board includes steps of forming a groove portion in an outer periphery portion of a support metal foil provided metal foil in a shape of frame, in which a metal foil is held on the support metal foil with a release layer interposed between them, mounting the support metal foil provided metal foil on a principal surface of a support board containing an uncured thermosetting resin, pressing and heating them, forming a laminated body on an upper surface of the metal foil located at least in an inside region of the groove portion, cutting out the laminated body and the support board located in the inside region, and separating the laminated body from the support metal foil.Type: ApplicationFiled: December 15, 2014Publication date: July 9, 2015Applicant: KYOCERA CIRCUIT SOLUTIONS, INC.Inventor: Masaharu YASUDA
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Patent number: 9018656Abstract: The light emitting device comprises a mounting substrate and an LED chip which comprises an n-type nitride semiconductor layer, a nitride light emission layer on the n-type nitride semiconductor layer, p-type nitride semiconductor layer on the nitride light emission layer, an anode electrode opposite of the nitride light emission layer from the p-type nitride semiconductor layer, and a cathode electrode on the n-type nitride semiconductor layer. The mounting substrate has a patterned conductor which is connected to the cathode electrode through a bump and also connected to the anode electrode through a bump. The LED chip further comprises one or more dielectric layer between the p-type nitride semiconductor layer and the anode electrode to have an arrangement which resembles an island. The p-type nitride semiconductor layer has a first region which is overlapped with the bump. The dielectric layer is not formed within the first region.Type: GrantFiled: February 23, 2010Date of Patent: April 28, 2015Assignee: Panasonic CorporationInventors: Akihiko Murai, Masaharu Yasuda, Tomoya Iwahashi, Kazuyuki Yamae
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Publication number: 20140182126Abstract: A method for manufacturing a wiring board according to the present invention includes the steps of preparing a supporting substrate having a product forming region and a marginal region; preparing a separable metal foil whose area is larger than that of the product forming region and is smaller than that of the supporting substrate; fixing the separable metal foil to the supporting substrate by burying into the supporting substrate; forming a build-up section on the buried separable metal foil; integrally cutting out the supporting substrate, the separable metal foil and the build-up section; obtaining a laminated body for wiring board composed of the second metal foil and the build-up section by separating the first metal foil and the second metal foil; and forming the wiring conductor layer by removing a part of the second metal foil.Type: ApplicationFiled: December 10, 2013Publication date: July 3, 2014Applicant: KYOCERA SLC Technologies CorporationInventors: Daisuke NARUMI, Yoshinori NAKATOMI, Masaharu YASUDA
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Patent number: 8525204Abstract: A semiconductor light emitting element, including: an n-type semiconductor layer having optical transparency with an emission wavelength of a light emitting layer, the light emitting layer and a p-type semiconductor layer, which are laminated; and a reflection film which is disposed on a side opposite to a surface from which light emitted from the light emitting layer is extracted, wherein the reflection film comprises: a transparent layer having optical transparency with the emission wavelength of the light emitting layer, and a metal layer, which is laminated on the transparent layer on a side opposite to the light emitting layer and is constituted by a metal material having a high reflectance, the transparent layer has a refractive index lower than a refractive index of a layer disposed on a side of the light emitting layer when viewed from the transparent layer, with the emission wavelength, and a thickness of the transparent layer is equal to or more than a value obtained by dividing a value of ¾ of theType: GrantFiled: March 25, 2009Date of Patent: September 3, 2013Assignee: Panasonic CorporationInventors: Hiroshi Fukshima, Kazuyuki Yamae, Masaharu Yasuda, Tomoya Iwahashi, Akihiko Murai
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Patent number: 8399272Abstract: A method of manufacturing the semiconductor light emitting element comprises a semiconductor layer forming step of forming the multilayered nitride semiconductor layer on the first wafer having a transparent property; a bonding step of bonding the multilayered nitride semiconductor layer to the first wafer; a groove forming step of forming the groove extending from the lower surface of the first wafer to the multilayered nitride semiconductor layer; a light applying step of applying a first light to the lower surface of the multilayered nitride semiconductor layer through the first wafer to reduce a bonding force between the multilayered nitride semiconductor layer and the first wafer; a separating step of separating the first wafer from the multilayered nitride semiconductor layer; and a cutting step of cutting the second wafer along the groove to divide into a plurality of the semiconductor light emitting element.Type: GrantFiled: October 27, 2009Date of Patent: March 19, 2013Assignee: Panasonic CorporationInventors: Kazuyuki Yamae, Hiroshi Fukshima, Masaharu Yasuda, Tomoya Iwahashi, Hidenori Kamei, Syuusaku Maeda
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Patent number: 8367442Abstract: A method of manufacturing the semiconductor light emitting element comprises a semiconductor layer forming step of forming the multilayered nitride semiconductor layer on the first wafer having a transparent property; a bonding step of bonding the multilayered nitride semiconductor layer to the first wafer; a groove forming step of forming the groove extending from the lower surface of the first wafer to the multilayered nitride semiconductor layer; a light applying step of applying a first light to the lower surface of the multilayered nitride semiconductor layer through the first wafer to reduce a bonding force between the multilayered nitride semiconductor layer and the first wafer; a separating step of separating the first wafer from the multilayered nitride semiconductor layer; and a cutting step of cutting the second wafer along the groove to divide into a plurality of the semiconductor light emitting element.Type: GrantFiled: October 27, 2009Date of Patent: February 5, 2013Assignee: Panasonic CorporationInventors: Kazuyuki Yamae, Hiroshi Fukshima, Masaharu Yasuda, Tomoya Iwahashi, Hidenori Kamei, Syuusaku Maeda
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Publication number: 20110297989Abstract: The light emitting device comprises a mounting substrate and an LED chip which comprises an n-type nitride semiconductor layer, a nitride light emission layer on the n-type nitride semiconductor layer, p-type nitride semiconductor layer on the nitride light emission layer, an anode electrode opposite of the nitride light emission layer from the p-type nitride semiconductor layer, and a cathode electrode on the n-type nitride semiconductor layer. The mounting substrate has a patterned conductor which is connected to the cathode electrode through a bump and also connected to the anode electrode through a bump. The LED chip further comprises one or more dielectric layer between the p-type nitride semiconductor layer and the anode electrode to have an arrangement which resembles an island. The p-type nitride semiconductor layer has a first region which is overlapped with the bump. The dielectric layer is not formed within the first region.Type: ApplicationFiled: February 23, 2010Publication date: December 8, 2011Inventors: Akihiko Murai, Masaharu Yasuda, Tomoya Iwahashi, Kazuyuki Yamae
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Patent number: 8049233Abstract: A light-emitting device of the present invention includes: a semiconductor layer 1 including a light-emitting layer 12; a recess/projection portion 14 including recesses and projections formed in a pitch larger than a wavelength of light emitted from the light-emitting layer 12, the recess/projection portion 14 being formed in a whole area or a partial area of the surface of the semiconductor layer which light is emitted from; and a reflective layer formed on an opposite surface of the semiconductor layer to the surface from which light is emitted, the reflective layer having a reflectance of 90% or more. According to the light-emitting device having such arrangement, the light can be emitted efficiently by synergetic effect of the reflective layer and the recess/projection portion.Type: GrantFiled: March 9, 2007Date of Patent: November 1, 2011Assignee: Panasonic Electric Works Co., Ltd.Inventors: Hiroshi Fukshima, Masaharu Yasuda, Kazuyuki Yamae
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Publication number: 20110263058Abstract: A method of manufacturing the semiconductor light emitting element comprises a semiconductor layer forming step of forming the multilayered nitride semiconductor layer on the first wafer having a transparent property; a bonding step of bonding the multilayered nitride semiconductor layer to the first wafer; a groove forming step of forming the groove extending from the lower surface of the first wafer to the multilayered nitride semiconductor layer; a light applying step of applying a first light to the lower surface of the multilayered nitride semiconductor layer through the first wafer to reduce a bonding force between the multilayered nitride semiconductor layer and the first wafer; a separating step of separating the first wafer from the multilayered nitride semiconductor layer; and a cutting step of cutting the second wafer along the groove to divide into a plurality of the semiconductor light emitting element.Type: ApplicationFiled: October 27, 2009Publication date: October 27, 2011Applicants: Panasonic Corporation, Panasonic Electric Works Co., Ltd.Inventors: Kazuyuki Yamae, Hiroshi Fukshima, Masaharu Yasuda, Tomoya Iwahashi, Hidenori Kamei, Syuusaku Maeda
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Publication number: 20110018024Abstract: A semiconductor light emitting element, including: an n-type semiconductor layer having optical transparency with an emission wavelength of a light emitting layer, the light emitting layer and a p-type semiconductor layer, which are laminated; and a reflection film which is disposed on a side opposite to a surface from which light emitted from the light emitting layer is extracted, wherein the reflection film comprises: a transparent layer having optical transparency with the emission wavelength of the light emitting layer, and a metal layer, which is laminated on the transparent layer on a side opposite to the light emitting layer and is constituted by a metal material having a high reflectance, the transparent layer has a refractive index lower than a refractive index of a layer disposed on a side of the light emitting layer when viewed from the transparent layer, with the emission wavelength, and a thickness of the transparent layer is equal to or more than a value obtained by dividing a value of ¾ of theType: ApplicationFiled: March 25, 2009Publication date: January 27, 2011Applicant: PANASONIC ELECTRIC WORKS CO., LTD.Inventors: Hiroshi Fukshima, Kazuyuki Yamae, Masaharu Yasuda, Tomoya Iwahashi, Akihiko Murai
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Publication number: 20090267092Abstract: A light-emitting device of the present invention includes: a semiconductor layer 1 including a light-emitting layer 12; a recess/projection portion 14 including recesses and projections formed in a pitch larger than a wavelength of light emitted from the light-emitting layer 12, the recess/projection portion 14 being formed in a whole area or a partial area of the surface of the semiconductor layer which light is emitted from; and a reflective layer formed on an opposite surface of the semiconductor layer to the surface from which light is emitted, the reflective layer having a reflectance of 90% or more. According to the light-emitting device having such arrangement, the light can be emitted efficiently by synergetic effect of the reflective layer and the recess/projection portion.Type: ApplicationFiled: March 9, 2007Publication date: October 29, 2009Applicant: MATSUSHITA ELECTRIC WORKS, LTD.Inventors: Hiroshi Fukshima, Masaharu Yasuda, Kazuyuki Yamae
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Publication number: 20080051438Abstract: The present invention provides compositions that exert a superior hypotensive action while inhibiting an increase in heart rate. The present invention provides antihypertensives and preventive/therapeutic compositions useful in the treatment of cardiovascular diseases, which contain cilnidipine and at least one angiotensin II receptor blocker(s). The present invention also provides methods for treating cardiovascular diseases by administration of said compositions.Type: ApplicationFiled: August 13, 2007Publication date: February 28, 2008Inventors: Shinobu Nagahama, Takeo Norimatsu, Toshio Maki, Masaharu Yasuda, Shinsuke Tanaka
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Publication number: 20040164060Abstract: A method and apparatus for drilling a hole through a printed circuit board is described using a laser beam such that the diameter of the top portion and the bottom portion of the hole are substantially equal. The laser beam is irradiated perpendicularly to a printed circuit board to drill a tapered hole having a top portion and a bottom portion wherein the diameter of the bottom portion is smaller than that of the top portion. Further, the laser beam 10 is irradiated to the tapered hole obliquely relative to the board 12 to equalize the diameters of the top and bottom portions to each other. By irradiating the laser beam 10 obliquely, a straight hole 14 can be formed.Type: ApplicationFiled: February 20, 2004Publication date: August 26, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yoji Maeda, Yutaka Tsukada, Kimihiro Yamanaka, Masaharu Yasuda