Abstract: This invention aims to perform mapping in a user space without concern for an architecture of a parallel computer and to obtain a high-speed mapping pattern. An N-dimensional model is divided by a user into a plurality of calculation units. The calculation units and physical processors are assigned with an identification code. Correspondence therebetween is held on an address conversion table. By accessing the address conversion table, the user can freely perform a mapping operation. Thereafter, interprocessor communication is carried out by the use of the identification code assigned to the calculation units.

Abstract: In a parallel computer system comprising a plurality of processor elements, a parent processor element generates random-number initial values, and distributes the random-number initial values to child processor elements using a communication mechanism or a shared memory; and child processor elements conduct processing to generate random-number sequences in accordance with the maximum length shift register sequence (M-sequence) method using the distributed random-number initial values as seeds.