Patents by Inventor Masahide Kanegae

Masahide Kanegae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5841602
    Abstract: Disclosed is a PRML regenerating apparatus for regenerating a signal read by a head from a storage medium. This PRML regenerating apparatus has a waveform equalizing circuit for waveform-equalizing the read signal, a maximum-likelihood decoder for maximum-likelihood-decoding, after obtaining a determination value by comparing the equalized output with upper and lower slice levels, this determination value and a control circuit for setting variable a distance between the upper slice level and the lower slice level of the maximum-likelihood decoder. The distance between the upper and lower slice levels can be thereby set variable in accordance with an equalization characteristic. A ternary determination circuit of the maximum-likelihood decoder is constructed of a memory for storing a correspondence table of the equalized output and the upper or lower slice level versus the determination result and the next upper or lower slice level.
    Type: Grant
    Filed: September 17, 1996
    Date of Patent: November 24, 1998
    Assignee: Fujitsu Limited
    Inventors: Masahide Kanegae, Masao Kondou
  • Patent number: 5825570
    Abstract: Disclosed is a PRML regenerating apparatus for regenerating a signal read by a head from a storage medium. This PRML regenerating apparatus has a waveform equalizing circuit for waveform-equalizing the read signal, a maximum-likelihood decoder for maximum-likelihood-decoding, after obtaining a determination value by comparing the equalized output with upper and lower slice levels, this determination value and a control circuit for setting variable a distance between the upper slice level and the lower slice level of the maximum-likelihood decoder. The distance between the upper and lower slice levels can be thereby set variable in accordance with an equalization characteristic. A ternary determination circuit of the maximum-likelihood decoder is constructed of a memory for storing a correspondence table of the equalized output and the upper or lower slice level versus the determination result and the next upper or lower slice level.
    Type: Grant
    Filed: September 16, 1996
    Date of Patent: October 20, 1998
    Assignee: Fujitsu Limited
    Inventors: Masahide Kanegae, Masao Kondou, Tomoki Sugaya, Hiroyuki Tanaka
  • Patent number: 5694265
    Abstract: A duty pulse is formed by setting in response to a leading edge of a clock synchronized with a peak detection of a servo frame read signal by a peak detecting circuit and by resetting by a signal by which a zero-cross point of a read signal of a phase servo pattern was detected. A head position signal is formed by integrating the duty pulse. Since there is a deviation of the timings between the peak detection and the zero-cross detection, a duty ratio is measured so as to be adjusted to 50% in the on-track state of a target cylinder. The timings for a reference clock and a zero-cross detection pulse are delayed and adjusted accordingly.
    Type: Grant
    Filed: August 30, 1994
    Date of Patent: December 2, 1997
    Assignee: Fujitsu Limited
    Inventors: Tatsuhiko Kosugi, Susumu Yoshida, Makoto Chiba, Syuichi Hashimoto, Masahide Kanegae
  • Patent number: 5689655
    Abstract: An apparatus for connecting and disconnecting a plurality of drives connected in parallel with respect to a data transmission line in a magnetic disk system, etc., to and from the data transmission line under an active state, has data communication terminals provided for each of the drives, so as to be connected to the data transmission line and disconnected from the data transmission line; and units for fixing the levels at the data communication terminals when the data communication terminals are open. Preferably, the units for fixing the levels includes resistors connected between the data communication terminals and a ground, the resistance of each of the resistors being determined not to disturb an impedance of the data transmission line.
    Type: Grant
    Filed: December 27, 1996
    Date of Patent: November 18, 1997
    Assignee: Fujitsu Limited
    Inventors: Hiroyuki Tanaka, Masahide Kanegae
  • Patent number: 5675446
    Abstract: A method of controlling a magnetic disk unit. The method controls the magnetic disk unit which comprises a disk enclosure part and a printed-circuit board part. The disk enclosure part includes at least one magnetic disk, at least one magnetic head and a mechanical part for driving each magnetic disk and each magnetic head. The printed-circuit board part includes a circuit part for controlling the disk enclosure part. The method includes the steps of writing on the magnetic disk version data indicating a type of disk enclosure part after the disk enclosure part and the printed-circuit board part are assembled, and automatically setting the circuit part of the printed-circuit board part depending on the version data which is read from the magnetic disk after the magnetic disk unit is completed.
    Type: Grant
    Filed: December 9, 1994
    Date of Patent: October 7, 1997
    Assignee: Fujitsu Limited
    Inventors: Tatsuhiko Kosugi, Masahide Kanegae, Nobuyuki Suzuki
  • Patent number: 5440434
    Abstract: In a reproduced waveform equalizing circuit for thin-film magnetic heads for eliminating a negative edge of a thin-film magnetic head, even if there is a manufactural variation in thin-film magnetic heads, the negative edge is eliminated. In the reproduced waveform equalizing circuit, an operation circuit receives a readout output including a negative edge from a selected one of a plurality of thin-film magnetic heads and performs waveform equalization from the output of a delay circuit. The output delay circuit has an input side terminated with a characteristic impedance and provides a time delay of (.tau.2-.tau.1), the output of a multiplier (4) for multiplying a (J2-J1) delayed signal by K1 and the output of a delay amount changing circuit (6) for delaying an input signal to eliminate a negative edge.
    Type: Grant
    Filed: May 3, 1993
    Date of Patent: August 8, 1995
    Assignee: Fujitsu Limited
    Inventor: Masahide Kanegae
  • Patent number: 5068753
    Abstract: A data recording and reproducing circuit for a memory system, such as a magnetic disk memory system. The circuit includes a reflection type cosine equalizer and a data reproducing circuit. The equalizer includes a first equalizing circuit, having a first equalizing gain, and outputting a first equalized signal, and a second equalizing circuit having a second equalizing gain smaller than the first equalizing gain, and outputting a second equalizing circuit. The data reproducing circuit includes a differentiator for differentiating the first equalized signal, a window generating circuit for generating a window signal from the second equalized signal, and a data separator for discriminating the differentiated signal in response to the window signal to produce a pulsed reproduction signal.
    Type: Grant
    Filed: March 15, 1989
    Date of Patent: November 26, 1991
    Assignee: Fujitsu Limited
    Inventor: Masahide Kanegae