Abstract: A pillar trim structure comprises: a vehicular pillar; a pillar trim for covering the pillar from the inner side of a compartment; a first retained member having its one end fixed on a vehicular widthwise face of the pillar trim and extended to the side of the pillar and its other end retained in a first hole formed in the pillar; and a second retained member having its one end fixed on the vehicular widthwise face of the pillar trim and extended to the side of the pillar and its other end retained in a second hole formed in the pillar. The engagements between the first and the second retained members, and the pillar can be released by deforming the pillar trim to separate the other end of the first retained member and the other end of the second retained member.

Abstract: A pillar trim structure comprises: a vehicular pillar; a pillar trim for covering the pillar from the inner side of a compartment; a first retained member having its one end fixed on the vehicular widthwise outer face of the pillar trim and extended to the side of the pillar and its other end retained in a first hole formed in the pillar; and a second retained member having its one end fixed on the vehicular widthwise outer face of the pillar trim and extended to the side of the pillar and its other end retained in a second hole formed in the pillar. The engagements between the first and the second retained members, and the pillar can be released by deforming the pillar trim to separate the other end of the first retained member and the other end of the second retained member.

Abstract: The present invention relates to an LSI which performs a self test using its built-in test function according to a test program stored in an on-chip memory. An object of the present invention is to efficiently perform the self test in the case where branching to an address out of the address space of the on-chip memory occurs. A program counter 101 stores addresses of a memory 117 and an external memory. A test program counter 108 stores an address of the memory 117. In a test mode, a program counter switching section 109 performs control so that when an address of the memory 117 is detected in the program counter 101, the address value of the program counter 101 is selected, whereas when an address of the external memory is detected in the program counter 101, the address value of the test program counter 108 is selected. A signature compression circuit 110 signature-compresses and holds the output value of the program counter 101.

Abstract: The present invention relates to an LSI which performs a self test using its built-in test function according to a test program stored in an on-chip memory. An object of the present invention is to efficiently perform the self test in the case where branching to an address out of the address space of the on-chip memory occurs.