Abstract: A painting pattern generation system for painting interior areas enclosed by outlines indicated by outline data and flag data. This includes a first memory for storing outline data, a second memory for storing flag data, and an operational circuit for reading out the outline data. The flag data in the first and the second memories performs a logical exclusive OR operation on adjacent items of the flag data in the second memory in a scan line direction, and performs an OR operation between the result of the logical exclusive OR operation and the outline data in the first memory in all of the scan line directions. Thus obtaining the painted pattern data, and a writing circuit for writing the painted pattern data obtained by the operational circuit to overlap it with subsequent outline data in the first memory.

Abstract: Coordinate values of control points of a given Bezier curve are stored in a register, the contents of the register are supplied to a determination circuit to determine whether a distance between adjacent control points can further be bisected into two parts. If bisecting processing can be performed, the contents of the register are supplied to a bisection circuit, the Bezier curve is subdivided into two parts to generate new Bezier curves, and control point data of one of the new Bezier curves is applied to a stack memory and that of the other new Bezier curve is sent to the register. The contents of the register are checked by the determination circuit each time the contents of the register are updated.

Abstract: A three-dimensional graphic processing apparatus includes n arithmetic ICs (Integrated Circuits) for performing linear interpolation calculations for each scan line of a triangle polygon to obtain intensity values and depth coordinate values of pixels, and two types of n memories for storing the calculation results. The n arithmetic ICs parallelly execute linear interpolation calculations of n different pixels successive on a single scan line of a single triangle polygon in one processing cycle. Each arithmetic IC calculates for each of every n pixels in one processing cycle, and a corresponding one of the memories stores the calculation result.

Abstract: A pattern data generating system has a processor for writing in a bit map memory, on the basis of input data, points of all lines to be filled or painted along a scan direction which is one direction on the bit map memory. This writing is performed such that a point on each line is written as one of the two end points of the line thereof while a point, offset by one point in the scan direction, is written as the other of the two end points of the line. The pattern data generating system also has a pattern data generating circuit for, if w (w is a positive integer) points b0, b1, . . . , b(w-2), and b(w-1) are present on one scan line, writing EXOR of data of points b0, b1, . . . , b(j-1) at positions corresponding to points b(j) (j is not less than 0 and less than w). Similar EXOR data writing is performed by the pattern data generating circuit for all the scan lines. Then, pattern data, in which the area surrounded by the closed curve is filled or painted, is obtained.

Abstract: A bit mask generator comprises partial mask generators for generating partial mask data corresponding to a plurality of blocks obtained by dividing input data, and parity correction circuits for correcting the partial mask data in accordance with a parity input and generating parity outputs. Each of the partial mask generators includes a plurality of first exclusive OR gates each of which receives bit data of a corresponding block as one input and input data of an LSB (Least Significant Bit) or an output of a lower-bit first exclusive OR gate as the other input. Each of the parity correction circuits includes a plurality of second exclusive OR gates each of which receives as one input the partial mask data generated by the partial mask generator of a corresponding block and as the other input a parity generated by a lower-bit parity correction circuit.

Abstract: A pattern data generating system comprises first and second bit map memories, a first control block for sequentially generating points corresponding to the boundaries of a closed curve in response to changes dx and dy along x and y directions, and writing the points in the first bit map memory, a second control block for sequentially generating points, which are required to paint an area enclosed by the closed curve, on the basis of the changes dx and dy, in accordance with a predetermined rule, and writing the points in the second bit map memory, a third control block for, if w (w is a positive integer) points b0, b1, . . . , b(w-2), and b(w-1) are present on a single scan line provided that one direction is set to be a scan direction on the second bit map memory, sequentially writing EXOR data of the points b0, b1, . . .

Abstract: A memory device having an operating function includes a memory cell array, a register, and a logical opeation circuit. The memory cell array has memory cells arranged in a matrix form of m rows .times.n columns. Data readout or write-in operation with respect to the memory cell array is effected in the unit of n bits of one row. The register has a bit width corresponding to one row of the memory cell array. Data of one row is read out from the memory cell array and is processed by the logical operation circuit together with data stored in the register. The result of operation is written into a desired row of the memory cell array. The memory cell array, register, and logical operation circuit are formed in the same integrated circuit, thus permitting processing such as picture element processing to be effected inside the integrated circuit, without the need to use an external data bus.

Abstract: A shading circuit has a unit for calculating coordinates and intensities of points inside a polygon based on X, Y, and Z coordinates and intensities of vertexes of each of polygons constituting a solid model. This unit includes a preprocessing section for obtaining the depth change .DELTA.Z/.DELTA.X of Z coordinate for each unit change in X coordinate and the change .DELTA.I/.DELTA.X of intensity for each unit change in X coordinate, based on X, Y, and Z coordinates and intensities of three vertexes of each of triangular polygons constituting a solid model, and a digital differential analyzer until for obtaining Z coordinates and intensities of points inside each polygon commonly using .DELTA.Z/.DELTA.X and .DELTA.I/.DELTA.X when the X and Y coordinates of the points are determined.

Abstract: The invention provides a full adder having a logic circuit which has an inverter and a selector circuit, a logic circuit which has an inverter and a selector circuit, and a logic circuit which has a selector circuit and an inverter so as to produce a sum output signal S and a carry output signal C in response to three input signals X, Y and Z.

Abstract: In an adder circuit in which the input data is divided into a plurality of bit blocks each consisting of a plurality of bits for parallel data processing, two adder sections with the carry inputs thereto respectively set to logic "0" and "1" are provided for each of the blocks other than the LSB block. The sum and carry outputs from each section in each block are commonly connected through a gate circuit, which is controlled by a carry output from the next lower bit block.

Abstract: A multiplication circuit includes a multiplying unit for multiplying a signed multiplier X represented in terms of the two's complement of n bits by a signed multiplicand Y represented in terms of two's complement of n bits to generate a signed multiplication output data of (2n-1) bits represented in terms of the two's complement, an exclusive-OR circuit for producing the exclusive-OR of the sign bits X.sub.S and Y.sub.S of the respective values X and Y, and a selecting circuit for generating a sign bit "0" when the most significant bit of the multiplication output data from the multiplying unit is "0" and generating as a sign bit an output bit of the exclusive-OR circuit when the most significant bit is "1".

Abstract: A data error correction circuit is provided, which receives input data having check bit data added thereto, the input data being divided by a generator polynomial G(x) in terms of the modulo 2 and multiplied by a correction polynomial M(x) in terms of modulo 2. An error in the input data is detected and corrected in accordance with contents of a syndrome obtained by these operations. The data error correction circuit includes a latch circuit and a presettable data input circuit. Data from the presettable data input circuit is divided by the generator polynomial G(x) in terms of the modulo 2, and remainder bit data obtained thereby is stored in the latch circuit as the correction polynomial M(x).

Abstract: A binary multiplication cell circuit suitable for a MOS transistor integrated circuit. The cell circuit has a NOR circuit for obtaining a partial product of one binary digit of a multiplicand and one binary digit of a multiplier and a full adder for obtaining result of multiplication (or augend) and a carry digit based on the partial product, an augend supplied from a given multiplication cell circuit and a carry digit supplied from another given multiplication cell circuit. The full adder comprises two AND circuits, three NOR circuits, an inverter and an exclusive OR circuit. Preferably, the exclusive OR circuit is constituted by an exclusive NOR circuit and an inverter.