Patents by Inventor Masahide Ouchi

Masahide Ouchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10031824
    Abstract: A detailed execution schedule of self-diagnosis processing is set according to various requests. A self-diagnosis device includes a plurality of functional blocks, a storage unit that stores a plurality of processing units, each of which is an aggregate of some functional blocks selected from the plurality of functional blocks, and a start condition of self-diagnosis processing of each processing unit, and a self-diagnosis unit that selects the processing unit where the self-diagnosis processing is started based on the start condition of each processing unit and executes the self-diagnosis processing of each functional block in the selected processing unit.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: July 24, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masahide Ouchi
  • Publication number: 20180089046
    Abstract: A semiconductor device includes a plurality of functional blocks, and a self-diagnosis circuit that controls a test for the functional blocks. When an interruption request is issued, the self-diagnosis circuit executes a test for one of the functional blocks.
    Type: Application
    Filed: November 2, 2017
    Publication date: March 29, 2018
    Inventor: Masahide Ouchi
  • Patent number: 9836374
    Abstract: A detailed execution schedule of self-diagnosis processing is set according to various requests. A self-diagnosis device includes a plurality of functional blocks, a storage unit that stores a plurality of processing units, each of which is an aggregate of some functional blocks selected from the plurality of functional blocks, and a start condition of self-diagnosis processing of each processing unit, and a self-diagnosis unit that selects the processing unit where the self-diagnosis processing is started based on the start condition of each processing unit and executes the self-diagnosis processing of each functional block in the selected processing unit.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: December 5, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masahide Ouchi
  • Publication number: 20150261637
    Abstract: A detailed execution schedule of self-diagnosis processing is set according to various requests. A self-diagnosis device includes a plurality of functional blocks, a storage unit that stores a plurality of processing units, each of which is an aggregate of some functional blocks selected from the plurality of functional blocks, and a start condition of self-diagnosis processing of each processing unit, and a self-diagnosis unit that selects the processing unit where the self-diagnosis processing is started based on the start condition of each processing unit and executes the self-diagnosis processing of each functional block in the selected processing unit.
    Type: Application
    Filed: March 4, 2015
    Publication date: September 17, 2015
    Inventor: Masahide Ouchi
  • Patent number: 8421504
    Abstract: A microcomputer includes a first comparator which compares a voltage to be monitored, with a first reference voltage, a second comparator which compares the voltage to be compared, with a second reference voltage, and an interrupt control circuit which monitors the voltage to be monitored by the first and second comparators in parallel and, when a preset condition is satisfied, generates an interrupt signal.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: April 16, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Masahide Ouchi
  • Publication number: 20110115526
    Abstract: A microcomputer includes a first comparator which compares a voltage to be monitored, with a first reference voltage, a second comparator which compares the voltage to be compared, with a second reference voltage, and an interrupt control circuit which monitors the voltage to be monitored by the first and second comparators in parallel and, when a preset condition is satisfied, generates an interrupt signal.
    Type: Application
    Filed: October 29, 2010
    Publication date: May 19, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Masahide Ouchi