Abstract: A gate electrode or a gate wiring of a thin-film transistor has a four-layer structure including an adhesive base layer, a catalyst layer, a wiring metal layer, and a wiring metal anti-diffusion layer which are laminated in this order. With this structure, adhesion and flatness are improved. In this case, the adhesive base layer is formed by a resin having a structure capable of coordinating to a metal. Hence, adhesion with an insulating substrate can be improved. Further, the wiring metal anti-diffusion layer is formed on the wiring metal layer, so that diffusion of a wiring metal can be inhibited. Thus, characteristics of the thin-film transistor can be improved.

Abstract: An erasable programmable read-only memory with NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and a series array of memory cell transistors, and a switching transistor connected between the series array of memory cell transistors and ground. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data writing mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive, so that this cell block is connected to the corresponding bit line. Under such a condition, a decoder circuit stores a desired data (a logic "one" e.g.

Abstract: An erasable programmable read-only memory (EPROM) with a NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and memory cell transistors connected in series. Word lines are connected to control gates of the cell transistors. In a data write mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive to connect the cell block to the corresponding bit line.

Abstract: An electrically erasable programmable read-only memory has an array of programmable memory cells connected to parallel bit lines on a semiconductive substrate. The memory cells include NAND cell blocks each of which has a first selection transistor coupled to a corresponding bit line, a second selection transistor coupled to the ground potential, and a series array of memory cell transistors each having a floating gate and a control gate. Word lines are respectively connected to the control gates of the memory cell transistors. In a data read mode, a selection transistor of a certain NAND cell block including a selected memory cell transistor is rendered conductive to connect this cell block to a bit line associated therewith.

Abstract: An erasable programmable read-only memory with a NAND cell structure including NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and memory cell transistors connected is series. Word lines are connected to control gates of the cell transistors. In a data write mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive to connect the cell block to the corresponding bit line.

Abstract: An ultraviolet beam from an ultraviolet radiation source is projected to an object having a fluorescent substance such as an adhesive-applied position on a continuous sheet of paper which is being transported and the luminous emission from the fluorescent substance is detected by light reception elements in a detection unit. In this case, at least more than two light reception elements are provided and the arithmetic process of the value of the output from each of the light reception elements is executed by a control computer disposed in a device main body. The value thus obtained is compared with a comparison value stored in storage means, thereby detecting the failure or the degree of adhesive application. When the failure of adhesive application is detected, an alarm buzzer is actuated while a lamp is turned on.