Abstract: According to one embodiment, a magnetic memory device includes a first insulating film provided on a semiconductor region, and having a portion located in a memory cell array area and thicker than a portion located in a peripheral circuit area, a plurality of conductive plugs located in the memory cell array area and provided in the first insulating film, stacked structures located in the memory cell array area, provided on the conductive plugs, and each having layers including a magnetic layer, and transistors located in the peripheral circuit area, and each including a gate electrode provided on the semiconductor region and covered with the first insulating film, wherein a thickness t0 from a main surface of the semiconductor region to a lower surface of each stacked structure is greater than a predetermined value.

Abstract: According to one embodiment, a magnetic memory device includes a first insulating film provided on a semiconductor region, and having a portion located in a memory cell array area and thicker than a portion located in a peripheral circuit area, a plurality of conductive plugs located in the memory cell array area and provided in the first insulating film, stacked structures located in the memory cell array area, provided on the conductive plugs, and each having layers including a magnetic layer, and transistors located in the peripheral circuit area, and each including a gate electrode provided on the semiconductor region and covered with the first insulating film, wherein a thickness t0 from a main surface of the semiconductor region to a lower surface of each stacked structure is greater than a predetermined value.

Abstract: According to one embodiment, a magnetic memory is disclosed. The magnetic memory includes a substrate, a first magnetoresistive element provided on the substrate. A second magnetoresistive element which is provided on the substrate and is arranged next to the first magnetoresistive element. Each of the first and second magnetoresistive elements includes a first magnetic layer, a tunnel barrier layer and a second magnetic layer. The tunnel barrier layer is provided on the first magnetic layer, the second magnetic layer is provided on the tunnel barrier layer. A first stress member having a tensile stress as an internal stress is provided on an area including a side face of the stacked body.

Abstract: According to one embodiment, a semiconductor device includes an interconnect provided on a first interlayer insulating film covering a semiconductor substrate in which an element is formed, a cap layer provided on the upper surface of the interconnect, and a barrier film provided between the interconnect and a second interlayer insulating film covering the interconnect. The interconnect includes a high-melting-point conductive layer, and the width of the interconnect is smaller than the width of the cap layer. The barrier film includes a compound of a contained element in the high-melting-point conductive layer.

Abstract: According to one embodiment, a semiconductor device includes an interconnect provided on a first interlayer insulating film covering a semiconductor substrate in which an element is formed, a cap layer provided on the upper surface of the interconnect, and a barrier film provided between the interconnect and a second interlayer insulating film covering the interconnect. The interconnect includes a high-melting-point conductive layer, and the width of the interconnect is smaller than the width of the cap layer. The barrier film includes a compound of a contained element in the high-melting-point conductive layer.

Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, and oxidizing at least part of the metal film with oxidizing species remaining in the insulating film.

Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, and oxidizing at least part of the metal film with oxidizing species remaining in the insulating film.

Abstract: An embodiment of the present invention provides a method for manufacturing a semiconductor device. This method comprises: forming a seed film at least on an inner face of a recessed portion of a substrate; forming a protection film on the seed film, the protection film being made of a material that is more easily oxidized than a material forming the seed film; heat-treating the protection film; exposing at least part of the seed film by removing at least part of the heat-treated protection film; forming a plating film on the seed film through electrolytic plating to be buried in the recessed portion, by supplying current to the seed film that is at least partially exposed; and removing the plating film except for a portion buried in the recessed portion.

Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a first metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, oxidizing at least part of the first metal film with oxidizing species remaining in the insulating film, and forming a second metal film, which includes any of a high melting point metal and a noble metal, on the first metal film, the first metal film and the second metal film sharing different metallic material.

Abstract: A stress analysis method is provided: including dividing, by using a division unit, an inside of a chip into a plurality of analysis areas, deriving, by using a composite property derivation unit, a composite property into which physical property values of a plurality of materials included in an analysis area are compounded, about each of the plurality of analysis areas on the basis of wiring structure data for each of the plurality of analysis areas, and creating, by using a stress analysis unit, a three-dimensional model of a finite element method which uses each analysis area as an element, to apply the composite property to each element, and to perform a stress analysis.

Abstract: A semiconductor device including at least two layers of interlayer-insulator-films stacked above a substrate and at least partially formed by a low-relative-dielectric-constant-film having a relative-dielectric-constant of 3.

Abstract: A semiconductor device includes an interlayer insulating film formed above a semiconductor substrate. The interlayer insulating film has a concave portion. A barrier metal layer is formed along a bottom and a sidewall of the concave portion. The barrier metal layer has a first portion provided along the sidewall of the concave portion and a second portion provided along the bottom of the concave portion. A metal wiring layer is formed in the concave portion via the barrier metal layer. The first portion of the barrier metal layer is composed of a titanium nitride layer whose titanium content is more than 50 at %, and the second portion of the barrier metal layer is composed of a titanium nitride layer whose titanium content is relatively larger than the titanium content of the first portion or of a Ti layer.

Abstract: A method for manufacturing a semiconductor device includes heating a substrate having an insulation film thereon to a first substrate temperature so that oxidizing species are emitted from the insulating film, the insulating film having a recessed portion formed in a surface thereof, forming a metal film on the insulating film at a second substrate temperature lower than the first substrate temperature, and oxidizing at least part of the metal film with oxidizing species remaining in the insulating film.

Abstract: A piezoelectric thin film device includes an amorphous metal film disposed on a substrate and a piezoelectric film disposed on the amorphous metal. One of crystal axis of the piezoelectric film is aligned in a direction perpendicular to a surface of the amorphous metal.

Abstract: An embodiment of the present invention provides a method for manufacturing a semiconductor device. This method comprises: forming a seed film at least on an inner face of a recessed portion of a substrate; forming a protection film on the seed film, the protection film being made of a material that is more easily oxidized than a material forming the seed film; heat-treating the protection film; exposing at least part of the seed film by removing at least part of the heat-treated protection film; forming a plating film on the seed film through electrolytic plating to be buried in the recessed portion, by supplying current to the seed film that is at least partially exposed; and removing the plating film except for a portion buried in the recessed portion.

Abstract: A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.

Abstract: A method for fabricating a semiconductor device, includes forming a first dielectric film above a substrate, forming an opening in the first dielectric film, forming a catalytic characteristic film using at least one of a metal having catalytic characteristics and a conductive oxide having catalytic characteristics as its material on sidewalls and at a bottom of the opening, depositing a conductive material film using a conductive material in the opening in which the catalytic characteristic film is formed on the sidewalls and at the bottom, removing the catalytic characteristic film formed on the sidewalls of the opening, and forming a second dielectric film above the first dielectric film and the conductive material film after the removing.

Abstract: A method for manufacturing a semiconductor device includes forming, on a substrate having a recessed portion on a surface, a plating film which is at least buried in the recessed portion and has a higher impurity concentration in an upper portion than in a lower portion, thermally treating the plating film, and removing the thermally treated plating film except for a portion buried in the recessed portion.

Abstract: A semiconductor device includes an effective wire formed above a substrate in a multilayer interconnection structure and having a first electrode pad in a top layer; a first reinforcing material formed in the multilayer interconnection structure like surrounding the effective wire; a protective film configured to protect a final surface of the multilayer interconnection structure; and a second reinforcing material formed at a position in contact with the protective film and also between an area in which the effective wire is formed and a chip area end, the second reinforcing material being constituted by a film pattern whose Young's modulus is larger than that of a conductor constituting the first electrode pad and that of a conductor constituting the first reinforcing material.

Abstract: A semiconductor device includes an effective wire formed above a substrate in a multilayer interconnection structure and having a first electrode pad in a top layer; a first reinforcing material formed in the multilayer interconnection structure like surrounding the effective wire; a protective film configured to protect a final surface of the multilayer interconnection structure; and a second reinforcing material formed at a position in contact with the protective film and also between an area in which the effective wire is formed and a chip area end, the second reinforcing material being constituted by a film pattern whose Young's modulus is larger than that of a conductor constituting the first electrode pad and that of a conductor constituting the first reinforcing material.