Abstract: An asynchronous data holding circuit including a source synchronizer which acquires an enable signal synchronized with a destination clock, in response to a rising or falling edge of the enable signal, acquires the other one of the rising or falling edge of the enable signal in synchronization with a source clock, and outputs the enable signal, a first data holding unit which holds a data signal from the source, in response to the enable signal from the source synchronizer and the source clock, a destination synchronizer which outputs the enable signal from the source synchronizer, in synchronization with the destination clock, and a second data holding unit which holds the data signal in the first data holding unit in response to the enable signal from the destination synchronizer and the destination clock, is provided.

Abstract: Problem: A master cannot use a built-in memory as an independent memory in the case where a memory does not use peripherals. Solution: A memory control apparatus includes main memories (for example, RAM) 35-1, 35-2, peripherals 40-1, 40-2 having built-in memories (for example, RAM) 43-1, 43-2, a master 20 for accessing the main memoirs and the built-in memories, and a access mode setting register for setting the access mode of the access object. Furthermore, the memory control apparatus includes an address decoder 31 for decoding an address from the master 20 and outputting the decoding results, and selectors 42-1, 42-2 for selecting access information including the decoding results being given to the built-in memories corresponding to the set access mode.

Abstract: An asynchronous data holding circuit including a source synchronizer which acquires an enable signal synchronized with a destination clock, in response to a rising or falling edge of the enable signal, acquires the other one of the rising or falling edge of the enable signal in synchronization with a source clock, and outputs the enable signal, a first data holding unit which holds a data signal from the source, in response to the enable signal from the source synchronizer and the source clock, a destination synchronizer which outputs the enable signal from the source synchronizer, in synchronization with the destination clock, and a second data holding unit which holds the data signal in the first data holding unit in response to the enable signal from the destination synchronizer and the destination clock, is provided.