Patents by Inventor Masahiko Hori

Masahiko Hori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11769715
    Abstract: The semiconductor device of the present embodiment includes a lead frame having a projection portion, the projection portion having an upper face and a side face, a semiconductor chip provided above the projection portion, and a bonding material provided between the projection portion and the semiconductor chip, the bonding material being in contact with the upper face and the side face, the bonding material bonding the lead frame and the semiconductor chip.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: September 26, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Masanari Seki, Daisuke Koike, Masahiko Hori
  • Publication number: 20230088828
    Abstract: According to one embodiment, a semiconductor device includes: a substrate; a first MOSFET and a second MOSFET that are provided on a first surface of the substrate and have sources commonly coupled; a third MOSFET and a fourth. MOSFET that are provided on the first surface of the substrate and have sources commonly coupled; a light receiver that is provided on the first surface of the substrate and is coupled to the first MOSFET, the second MOSFET, the third MOSFET, and the fourth MOSFET; and a light emitter that is provided on the light receiver.
    Type: Application
    Filed: March 4, 2022
    Publication date: March 23, 2023
    Applicants: KABUSHIKI KAISHA TOSHIBA, Toshiba Electronic Devices & Storage Corporation
    Inventors: Jia LIU, Masahiko HORI
  • Publication number: 20230089737
    Abstract: According to one embodiment, a semiconductor device includes: a substrate that has a first surface extending in a first direction and a second direction; a first metal oxide semiconductor field effect transistor (MOSFET) that is provided on the first surface of the substrate; a support base that is provided above the first surface of the substrate and extends in a third direction intersecting the first direction and the second direction; a light receiving element that is in contact with a second surface of the support base facing the first direction; and a light emitting element that is in contact with a third surface of the light receiving element facing the first direction.
    Type: Application
    Filed: February 17, 2022
    Publication date: March 23, 2023
    Applicants: KABUSHIKI KAISHA TOSHIBA, Toshiba Electronic Devices & Storage Corporation
    Inventors: Jia LIU, Masahiko HORI
  • Patent number: 11611009
    Abstract: According to one or more embodiments, a semiconductor device includes a mounting substrate and a semiconductor element on the mounting substrate. The mounting substrate has a first electrode pad and a second electrode pad. The semiconductor element has a supporting substrate, third and fourth electrode pads, first slits and second slits. The third and fourth electrode pads are provided on a first surface of the supporting substrate facing the mounting substrate. The first slits are provided both in the supporting substrate and in the third electrode pad. The second slits are provided both in the supporting substrate and in the fourth electrode pad. The semiconductor device further includes a first conductive bonding agent that connects the first electrode pad to the third electrode pad and a second conductive bonding agent that connects the second electrode pad to the fourth electrode pad.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: March 21, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Masahiko Hori, Tatsuo Tonedachi, Yoshinari Tamura, Mami Fujihara
  • Publication number: 20230080478
    Abstract: A semiconductor package includes a PDA chip, a MOS chip, and a wiring plate including a first principal surface and a second principal surface, the first principal surface being provided with a first rigid plate that is non-conductive and a second rigid plate that is conductive, the PDA chip being fixed to the first rigid plate by using a non-conductive bonding agent, a lower surface terminal of the MOS chip being soldered to the second rigid plate, the second principal surface being provided with an input terminal and an output terminal, the input terminal being electrically connected to the PDA chip, the output terminal being electrically connected to the second rigid plate.
    Type: Application
    Filed: February 22, 2022
    Publication date: March 16, 2023
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Jia LIU, Toshihiro TSUJIMURA, Masahiko HORI, Tatsuo TONEDACHI
  • Publication number: 20220406980
    Abstract: A semiconductor device includes an insulating member; a light-receiving element on a front surface of the insulating member; a light-emitting element on the light-receiving element; a first metal terminal electrically connected to the light-emitting element and provided on a back surface of the insulating member; a switching element mounted on the front surface via a metal pad, the switching element being electrically connected to the light-receiving element; and a second metal terminal provided on the back surface and electrically connected to the switching element via the metal pad. The insulating member has a first thickness in a first direction directed from the back surface toward the front surface. The metal pad has a second thickness in the first direction. The second metal terminal has a third thickness in the first direction. The first thickness is less than a combined thickness of the second and third thicknesses.
    Type: Application
    Filed: February 9, 2022
    Publication date: December 22, 2022
    Inventors: Mami FUJIHARA, Masahiko HORI
  • Publication number: 20220302337
    Abstract: According to one or more embodiments, a semiconductor device includes a mounting substrate and a semiconductor element on the mounting substrate. The mounting substrate has a first electrode pad and a second electrode pad. The semiconductor element has a supporting substrate, third and fourth electrode pads, first slits and second slits. The third and fourth electrode pads are provided on a first surface of the supporting substrate facing the mounting substrate. The first slits are provided both in the supporting substrate and in the third electrode pad. The second slits are provided both in the supporting substrate and in the fourth electrode pad. The semiconductor device further includes a first conductive bonding agent that connects the first electrode pad to the third electrode pad and a second conductive bonding agent that connects the second electrode pad to the fourth electrode pad.
    Type: Application
    Filed: September 2, 2021
    Publication date: September 22, 2022
    Inventors: Masahiko HORI, Tatsuo TONEDACHI, Yoshinari TAMURA, Mami FUJIHARA
  • Publication number: 20220246504
    Abstract: The semiconductor device of the present embodiment includes a lead frame having a projection portion, the projection portion having an upper face and a side face, a semiconductor chip provided above the projection portion, and a bonding material provided between the projection portion and the semiconductor chip, the bonding material being in contact with the upper face and the side face, the bonding material bonding the lead frame and the semiconductor chip.
    Type: Application
    Filed: April 22, 2022
    Publication date: August 4, 2022
    Inventors: Masanari Seki, Daisuke Koike, Masahiko Hori
  • Patent number: 11342249
    Abstract: The semiconductor device of the present embodiment includes a lead frame having a projection portion, the projection portion having an upper face and a side face, a semiconductor chip provided above the projection portion, and a bonding material provided between the projection portion and the semiconductor chip, the bonding material being in contact with the upper face and the side face, the bonding material bonding the lead frame and the semiconductor chip.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: May 24, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Masanari Seki, Daisuke Koike, Masahiko Hori
  • Publication number: 20210074611
    Abstract: The semiconductor device of the present embodiment includes a lead frame having a projection portion, the projection portion having an upper face and a side face, a semiconductor chip provided above the projection portion, and a bonding material provided between the projection portion and the semiconductor chip, the bonding material being in contact with the upper face and the side face, the bonding material bonding the lead frame and the semiconductor chip.
    Type: Application
    Filed: February 10, 2020
    Publication date: March 11, 2021
    Inventors: Masanari Seki, Daisuke Koike, Masahiko Hori
  • Publication number: 20190326248
    Abstract: A semiconductor device of an embodiment includes a substrate including a semiconductor element, a first electrode on the substrate and electrically connected to the semiconductor element, a second electrode on the substrate and electrically connected to the semiconductor element, and a terminal spaced from the first electrode, the substrate, and the second electrode. A first bonding wire has a first bonding portion bonded to the second electrode at a first end and a second bonding portion bonded to the terminal at a second end. A second bonding wire has a third bonding portion bonded to the second electrode at a first end and a fourth bonding portion bonded to the terminal at a second end. Each of the first and second bonding wires comprise copper and have a diameter less than or equal to 100 ?m.
    Type: Application
    Filed: February 28, 2019
    Publication date: October 24, 2019
    Inventors: Masahiko HORI, Hiroshi SHIBATA, Tsutomu SANO, Kazuya MARUYAMA
  • Patent number: 8872350
    Abstract: A semiconductor device containing: a semiconductor element; a support substrate; an insulating material layer for sealing the semiconductor element and a periphery thereof; a metal thin film wiring layer provided in the insulating material layer, with a part thereof being exposed on an external surface; and metal vias provided in the insulating material layer and electrically connected to the metal thin film wiring layer. The semiconductor element is provided in a plurality of units and the respective semiconductor elements are stacked via an insulating material such that a circuit surface of each semiconductor element faces the metal thin film wiring layer, and electrode pads of each semiconductor element are exposed without being hidden by the semiconductor element stacked thereabove.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: October 28, 2014
    Assignee: J-Devices Corporation
    Inventors: Shigenori Sawachi, Osamu Yamagata, Hiroshi Inoue, Satoru Itakura, Tomoshige Chikai, Masahiko Hori, Akio Katsumata
  • Publication number: 20130200523
    Abstract: A semiconductor device containing: a semiconductor element; a support substrate; an insulating material layer for sealing the semiconductor element and a periphery thereof; a metal thin film wiring layer provided in the insulating material layer, with a part thereof being exposed on an external surface; and metal vias provided in the insulating material layer and electrically connected to the metal thin film wiring layer. The semiconductor element is provided in a plurality of units and the respective semiconductor elements are stacked via an insulating material such that a circuit surface of each semiconductor element faces the metal thin film wiring layer, and electrode pads of each semiconductor element are exposed without being hidden by the semiconductor element stacked thereabove.
    Type: Application
    Filed: September 14, 2012
    Publication date: August 8, 2013
    Inventors: Shigenori SAWACHI, Osamu Yamagata, Hiroshi Inoue, Satoru Itakura, Tomoshige Chikai, Masahiko Hori, Akio Katsumata
  • Publication number: 20100230471
    Abstract: The bonding method for fanning a bump on an electrode on a substrate through bonding, includes: making a data storage part store a bonding position coordinate and an assumed bump-bonding area at the bonding position coordinate; recognizing a bondable area of the electrode by shooting an image of the electrode and processing the image; calculating overlap rate between the recognized bondable area and the assumed bump-bonding area stored in the data storage part; determining whether or not the calculated overlap rate is equal to or greater than a set value; and performing bonding on the bonding position coordinate when the overlap rate is determined to be equal to or greater than the set value. The bonding can be performed without being affected by the quality of finish of the electrode pads, and it is possible to avoid a bonding failure at flip-chip bonding and the like.
    Type: Application
    Filed: March 4, 2010
    Publication date: September 16, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Masahiko Hori
  • Publication number: 20100089204
    Abstract: A process for producing Ti, comprising a reduction step of reacting TiCl4 with Ca in a CaCl2-containing molten salt having the Ca dissolved therein to thereby form Ti particles, a separation step of separating the Ti particles formed in said molten salt from said molten salt and an electrolysis step of electrolyzing the molten salt so as to increase the Ca concentration, wherein the molten salt increased in Ca concentration in the electrolysis step is introduced into a regulating cell to thereby render the Ca concentration of the molten salt constant and thereafter the molten salt is used for the reduction of TiCl4 in the reduction step. In the present invention, the Ca concentration of the molten salt to be fed to the corresponding reduction vessel can be inhibited from fluctuating and, at the same time, can maintain high concentration levels. Further, a large volume of the molten salt can be treated continuously.
    Type: Application
    Filed: August 22, 2006
    Publication date: April 15, 2010
    Applicant: SUMITOMO TITANIUM CORPORATION
    Inventors: Tadashi Ogasawara, Makoto Yamaguchi, Toru Uenishi, Masahiko Hori, Kazuo Takemura, Katsunori Dakeshita
  • Patent number: 7648560
    Abstract: The present invention is a method for producing Ti or a Ti alloy through reduction of TiCl4 by Ca, which can produce the high-purity metallic Ti or high-purity Ti alloy. A molten salt containing CaCl2 and having Ca dissolved therein is held in a reactor vessel, and a metallic chloride containing TiCl4 is reacted with Ca in the molten salt to generate Ti particles or Ti alloy particles in a molten CaCl2 solution, which allows enhancement of a feed rate of TiCl4 which is of a raw material of Ti, and also allows a continuous operation. Therefore, the high-purity metallic Ti or the high-purity Ti alloy can economically be produced with high efficiency. Further, the method by the present invention eliminates the need of replenishment of expensive metallic Ca and of the operation for separately handling Ca which is highly reactive and difficult to handle.
    Type: Grant
    Filed: October 6, 2004
    Date of Patent: January 19, 2010
    Assignee: Osaka Titanium Technologies Co., Ltd.
    Inventors: Tadashi Ogasawara, Makoto Yamaguchi, Masahiko Hori, Toru Uenishi, Katsunori Dakeshita
  • Publication number: 20090152122
    Abstract: The present invention provides a method for electrolyzing molten salt that can enhance the concentration of metal-fog forming metal in the molten salt by carrying out the electrolysis under conditions that the molten salt containing the chloride of metal-fog forming metal is supplied from one end of an electrolytic cell to a space between an anode and a cathode in a continuous or intermittent manner to provide a flow rate in one direction to the molten salt in the vicinity of the surface of the cathode and thus to allow the molten salt to flow in one direction in the vicinity of the surface of the cathode. According to the present invention, while high current efficiency is maintained, only the molten salt enriched with metal-fog forming metal such as Ca can be effectively taken out. Further, this method can easily be carried out by using the electrolytic cell according to the present invention.
    Type: Application
    Filed: August 22, 2006
    Publication date: June 18, 2009
    Inventors: Tadashi Ogasawara, Makoto Yamaguchi, Toru Uenishi, Masahiko Hori, Kazuo Takemura, Katsunori Dakeshita
  • Publication number: 20090101517
    Abstract: In producing Ti or a Ti alloy through reduction by Ca, an electrolytic-bath salt taken out from a reduction process is electrolyzed to recover Ca and the electrolytic-bath salt as a solid substance, and the recovered Ca and electrolytic-bath salt are delivered to the reduction process. Therefore, heat generation is suppressed in the reduction process by utilizing latent heat of fusion possessed by the solid substance, thereby largely improving production efficiency and thermal efficiency. Additionally, a reaction temperature is easily controlled, and a raw-material loading rate can be enhanced to efficiently produce Ti or the Ti alloy. At this point, using a pulling electrolysis method of the invention, the solid-state Ca and electrolytic-bath salt can be obtained at a low voltage and high current efficiency, i.e., with the relatively small power consumption.
    Type: Application
    Filed: March 16, 2006
    Publication date: April 23, 2009
    Inventors: Kazuo Takemura, Tadashi Ogasawara, Makoto Yamaguchi, Masahiko Hori
  • Publication number: 20080250901
    Abstract: A TiCl4 gas is supplied to a molten CaCl2 liquid held in a reactor vessel 6 through a raw material feed pipe 11, TiCl4 is reduced to produce granular metallic Ti by Ca melted in the CaCl2 liquid. The molten CaCl2 liquid in which Ti granules taken out downward from the reactor vessel 6 is mixed is delivered to a separation process 12, the molten CaCl2 liquid is heated in a heating vessel 15, and separation is generated by a difference in specific gravity, whereby the molten CaCl2 liquid 16 is located in an upper layer while a metallic Ti 17 is located in a lower layer. The metallic Ti 17 in the lower layer is taken out from a high-melting-point metal discharge port 18, and the metallic Ti 17 is solidified to yield an ingot. The molten CaCl2 liquid 16 in the upper layer is delivered to an electrolysis process 13 along with the molten CaCl2 liquid taken out from the reactor vessel 6, and Ca generated by the electrolysis and CaCl2 are returned into the reactor vessel 6.
    Type: Application
    Filed: March 8, 2006
    Publication date: October 16, 2008
    Inventors: Tadashi Ogasawara, Makoto Yamaguchi, Katsunori Dakeshita, Masahiko Hori
  • Publication number: 20080217184
    Abstract: An apparatus for producing Ti by Ca reduction by the invention includes a reaction tank retaining a molten salt in which a molten salt CaCl2 is contained and Ca is dissolved, an electrolytic cell retaining a molten salt containing CaCl2, and a continuum body which is movably constructed while part of the continuum body is immersed in the molten salt either within the reaction tank or electrolytic cell. In the inventive method for producing Ti by Ca reduction, the molten salt in the electrolytic cell is electrolyzed to generate Ca on the cathode side which is transported to the reaction tank while deposited on and adheres to the continuum body, and TiCl4 is supplied to the reaction tank to generate Ti.
    Type: Application
    Filed: October 26, 2005
    Publication date: September 11, 2008
    Applicants: SUMITOMO TITANIUM CORPORATION, TOHOTITANIUM CO., LTD.
    Inventors: Masahiko Hori, Tadashi Ogasawara, Makoto Yamaguchi, Toru Uenishi, Masanori Yamaguchi, Yuichi Ono, Susumu Kosemura, Eiji Nishimura