Abstract: A semiconductor storage device of embodiments includes a block constituted with a plurality of strings each including a plurality of memory cell transistors, a plurality of word lines, a bit line, a source line, and a control circuit configured to perform erase operation on the plurality of memory cell transistors, and the control circuit changes setting of first erase-verify operation included in the erase operation for an open block including a memory cell transistor having an erase level and setting of second erase-verify operation included in erase operation for a closed block not including a memory cell transistor having an erase block.

Abstract: A semiconductor memory device performs a write operation and an erase operation. The write operation includes a first program operation that applies a first program voltage to a first conductive layer. The first program voltage increases by a first offset voltage together with an increase in an execution count of a first write loop. An erase operation includes a program voltage control operation and an erase voltage supply operation that applies an erase voltage to a first wiring. The program voltage control operation includes a second program operation that applies a second program voltage to a third conductive layer. The second program voltage increases by a second offset voltage together with an increase in a number of times of execution of a second write loop. A magnitude of the first program voltage is adjusted according to a magnitude of the second program voltage.

Abstract: A second conductor, third conductor, and fourth conductor sandwiches a first layer together with a first semiconductor. The fourth conductor is positioned farther from the first conductor than the third conductor, which is positioned farther from first conductor than the second conductor. A first circuit is configured to apply a first potential to the first and second conductors, apply a second potential lower than the first potential to the third conductor in parallel with the application of the first potential, and apply a third potential higher than the second potential and lower than the first potential to the fourth conductor in parallel with the application of the first potential.

Abstract: A semiconductor memory device includes a memory block with string units including a plurality of memory strings of memory cell transistors connected in series. Word lines are connected memory cell transistors in a same row and bit lines are respectively connected to one of the memory strings in each string unit. The bit lines are divided into different groups. A control circuit performs erasing on of the memory cell transistors in the memory block. The control circuit executes the erase verification on only a subset of memory strings in each string unit of the memory block rather than all memory strings.

Abstract: A semiconductor memory device includes a memory block with string units including a plurality of memory strings of memory cell transistors connected in series. Word lines are connected memory cell transistors in a same row and bit lines are respectively connected to one of the memory strings in each string unit. The bit lines are divided into different groups. A control circuit performs erasing on of the memory cell transistors in the memory block. The control circuit executes the erase verification on only a subset of memory strings in each string unit of the memory block rather than all memory strings.

Abstract: According to one embodiment, a semiconductor memory device includes a memory string including a first select transistor, a first transistor adjacent to the first select transistor, and a memory cell transistor, a first select gate line, a first interconnect, a word line, a row decoder, a temperature sensor, and a control circuit. In the erase operation, the control circuit selects a first mode for applying a first voltage to the first interconnect when a temperature measured by the temperature sensor is equal to or higher than a first temperature, and selects a second mode for applying a second voltage to the first interconnect when the temperature measured is less than the first temperature.

Abstract: According to one embodiment, a semiconductor memory device includes a memory string including a first select transistor, a first transistor adjacent to the first select transistor, and a memory cell transistor, a first select gate line, a first interconnect, a word line, a row decoder, a temperature sensor, and a control circuit. In the erase operation, the control circuit selects a first mode for applying a first voltage to the first interconnect when a temperature measured by the temperature sensor is equal to or higher than a first temperature, and selects a second mode for applying a second voltage to the first interconnect when the temperature measured is less than the first temperature.

Abstract: In a transmissivity inspection apparatus, laser beam is radiated onto an object to be inspected. Irregularly reflected laser light components produced from the object are detected by a photoelectric converter element. The transmissivity of the object with respect to the laser beam is inspected by a discriminator, based on a specific pattern of the irregularly reflected laser light components detected by the photoelectric converter element. The specific pattern of a transparent substance differs from that of a nontransparent substance, thereby to discriminate the nontransparent substance from the transparent substance.