Patents by Inventor Masahiko Ishiguri

Masahiko Ishiguri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8875895
    Abstract: The storage body includes a tape formed with recess portions that dip in in a thickness direction formed at intervals along the tape length direction and a cover that is superimposed on the tape and closes off openings of the recess portions. The tape is fixed to the tape by intermediate fixing portions and a pair of side fixing portions. The intermediate fixing portions are formed between the mutually adjacent recess portions. The pair of side fixing portions include overlapping portions and connect portions. The overlapping portions are formed at the two tape width direction sides of the intermediate fixing portions so as to overlap with the intermediate fixing portions along the tape length direction. The connect portions are formed with constant width connecting together the respective overlapping portions disposed in lines along the tape length direction.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: November 4, 2014
    Assignee: Fujitsu Limited
    Inventors: Keiichi Sasamura, Koichi Murata, Masahiko Ishiguri, Naoyuki Watanabe
  • Publication number: 20060258045
    Abstract: A semiconductor device includes a semiconductor substrate and an array of protruding electrodes arranged at a pitch X1. Each of the protruding electrodes has a height X3 and is formed on a barrier metal base of diameter X2 coupled to an electrode arranged on the semiconductor substrate so as to satisfy the relations (X½)?X2?(3*X¼) and (X½)?X3?(3*X¼).
    Type: Application
    Filed: April 27, 2006
    Publication date: November 16, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Masahiko Ishiguri, Hirohisa Matsuki, Hiroyuki Yoda, Tadahiro Okamoto, Masamitsu Ikumo, Shuichi Chiba
  • Patent number: 7095045
    Abstract: A semiconductor device includes a substrate, a pad electrode formed on the substrate and a bump electrode formed on the pad electrode, wherein the pad electrode has an irregular flaw, and there is provided a pattern covering the irregular flaw between the pad electrode an the bump electrode.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: August 22, 2006
    Assignee: Fujitsu Limited
    Inventors: Shuichi Chiba, Masahiko Ishiguri, Koichi Murata, Eiji Watanabe, Michiaki Tamagawa, Akira Satoh, Yasushi Toida, Kazuhiro Misawa
  • Patent number: 7064436
    Abstract: A semiconductor device includes a semiconductor substrate and an array of protruding electrodes arranged at a pitch X1. Each of the protruding electrodes has a height X3 and is formed on a barrier metal base of diameter X2 coupled to an electrode arranged on the semiconductor substrate so as to satisfy the relations (X1/2)?X2?(3*X1/4) and (X1/2)?X3?(3*X1/4).
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: June 20, 2006
    Assignee: Fujitsu Limited
    Inventors: Masahiko Ishiguri, Hirohisa Matsuki, Hiroyuki Yoda, Tadahiro Okamoto, Masamitsu Ikumo, Shuichi Chiba
  • Publication number: 20050151250
    Abstract: A semiconductor device includes a substrate, a pad electrode formed on the substrate and a bump electrode formed on the pad electrode, wherein the pad electrode has an irregular flaw, and there is provided a pattern covering the irregular flaw between the pad electrode an the bump electrode.
    Type: Application
    Filed: November 29, 2004
    Publication date: July 14, 2005
    Inventors: Shuichi Chiba, Masahiko Ishiguri, Koichi Murata, Eiji Watanabe, Michiaki Tamagawa, Akira Satoh, Yasushi Toida, Kazuhiro Misawa
  • Publication number: 20050140004
    Abstract: A semiconductor device includes a semiconductor substrate and an array of protruding electrodes arranged at a pitch X1. Each of the protruding electrodes has a height X3 and is formed on a barrier metal base of diameter X2 coupled to an electrode arranged on the semiconductor substrate so as to satisfy the relations (X1/2)?X2?(3*X1/4) and (X1/2)?X3?(3*X1/4).
    Type: Application
    Filed: November 23, 2004
    Publication date: June 30, 2005
    Inventors: Masahiko Ishiguri, Hirohisa Matsuki, Hiroyuki Yoda, Tadahiro Okamoto, Masamitsu Ikumo, Shuichi Chiba
  • Patent number: 6462415
    Abstract: There is provided a semiconductor device which comprises electrode pads formed on an insulating film on a semiconductor substrate, an insulating cover film formed on the insulating film to have openings that expose the electrode pads, and a masking tape having a base material layer and a resist layer coated on the base material layer, and for covering an upper surface of the cover film and inner surfaces of the openings in a situation that the resist layer is directed toward a semiconductor substrate side. Accordingly, it is possible to improve a throughput in a series of steps of grinding/polishing the semiconductor substrate and forming the bump electrodes which are required to thin the substrate of the semiconductor device.
    Type: Grant
    Filed: June 15, 2000
    Date of Patent: October 8, 2002
    Assignee: Fujitsu Limited
    Inventors: Masahiko Ishiguri, Eiji Watanabe, Yutaka Makino, Koichi Murata
  • Patent number: 5801439
    Abstract: A semiconductor device includes a semiconductor element, a package sealing the semiconductor element, and leads for passing signals between the semiconductor element and an external device. Each of the leads has an inner-lead part sealed within the package and connected with the semiconductor element, and an outer-lead part which extends outward from the package toward a top of the package, and is to be connected to the external device. The outer-lead part includes a first-port part at a lower side of the package, and a second-port part at an upper side of the package.
    Type: Grant
    Filed: February 21, 1997
    Date of Patent: September 1, 1998
    Assignee: Fujitsu Limited
    Inventors: Tetsuya Fujisawa, Mitsutaka Sato, Junichi Kasai, Masataka Mizukoshi, Kosuke Otokita, Hiroshi Yoshimura, Katsuhiro Hayashida, Akira Takashima, Masahiko Ishiguri, Michio Sono
  • Patent number: 5760471
    Abstract: A semiconductor device including a semiconductor element, and leads connected with the semiconductor element. Each of the leads includes an outer lead part for being connected externally. The semiconductor device further includes a plastic package sealing the semiconductor element and the leads. In the semiconductor device, the outer lead part is exposed to the outside of a side face of the plastic package, and the plastic package is mounted on any base in a standing form by the side face contacting the base.
    Type: Grant
    Filed: February 3, 1997
    Date of Patent: June 2, 1998
    Assignee: Fujitsu Limited
    Inventors: Tetsuya Fujisawa, Mitsutaka Sato, Junichi Kasai, Masataka Mizukoshi, Kousuke Otokita, Hiroshi Yoshimura, Katsuhiro Hayashida, Akira Takashima, Masahiko Ishiguri, Michio Sono