Abstract: An optical transceiver performs an optical transmitting and receiving operation, and has a first memory and an external interface. The external interface receives information from a host device and writes the received information in the first memory. The external interface reads the information from the first memory in response to an external command and transfers externally the read information. The information includes at least one of an operation start date, when the optical transceiver starts the optical transmitting and receiving operation, and an operation termination date, when the optical transceiver terminates the optical transmitting and receiving operation.

Abstract: A communication system comprises a transmitting device and a receiving device. The transmitting device includes means for connecting an addition bit string containing at least one bit 1 to information data, means for generating a CRC code corresponding to a remainder at a polynomial ring on a Galois field defined modulo 2 based on a predetermined generator polynomial of the information data connected with the addition bit string, means for transmitting the information data connected with the CRC code. The receiving device includes means for receiving the data, means for performing an addition of the data received and the addition bit string at a polynomial ring on a Galois field defined modulo 2, means for making a decision as to the presence or absence of a transmission error by determining the remainder at the polynomial ring on the Galois field defined modulo 2 based on the generator polynomial of data.

Abstract: An optical transceiver performs an optical transmitting and receiving operation, and has a first memory and an external interface. The external interface receives information from a host device and writes the received information in the first memory. The external interface reads the information from the first memory in response to an external command and transfers externally the read information. The information includes at least one of an operation start date, when the optical transceiver starts the optical transmitting and receiving operation, and an operation termination dates when the optical transceiver terminates the optical transmitting and receiving operation.

Abstract: A communication system comprises a transmitting device and a receiving device. The transmitting device includes means for connecting an addition bit string containing at least one bit 1 to information data, means for generating a CRC code corresponding to a remainder at a polynomial ring on a Galois field defined modulo 2 based on a predetermined generator polynomial of the information data connected with the addition bit string, means for transmitting the information data connected with the CRC code. The receiving device includes means for receiving the data, means for performing an addition of the received data and the addition bit string at a polynomial ring on a Galois field defined modulo 2, means for making a decision as to the presence or absence of a transmission error by determining the remainder at the polynomial ring on the Galois field defined modulo 2 based on the generator polynomial of data.

Abstract: A reference clock signal or a clock signal delayed in phase from the clock signal by ?/2 is input to D input terminal of a flip-flop circuit. An FSM receives signals input to the flip-flop circuits and signals which have been held by the flip-flop circuits, and outputs an up signal and a down signal. The flip-flop circuits and the FSM operate in synchronization only with a rising edge of a data signal.

Abstract: A reference clock signal or a clock signal delayed in phase from the clock signal by &pgr;/2 is input to D input terminal of a flip-flop circuit. An FSM receives signals input to the flip-flop circuits and signals which have been held by the flip-flop circuits, and outputs an up signal and a down signal. The flip-flop circuits and the FSM operate in synchronization only with a rising edge of a data signal.

Abstract: A hold circuit holds results of processing in an arithmetic circuit collectively receiving four bits from inputs. The inventive arithmetic unit collectively processes an input data string, which has generally been processed bit by bit, by four bits at a time, whereby a CRC arithmetic operation can be speeded up. More preferably, the arithmetic unit can flexibly deal with change of a generating polynominal set in the arithmetic circuit when rendering set data corresponding to the generating polynomial changeable.

Abstract: A counter circuit includes a plurality of flip flop circuits (FF circuits) sequentially connected for receiving a common clock signal, and two-input logic gates each having an input connected to an output of a corresponding FF circuit and the other input connected to an output of a common FF circuit, and of which output signal is supplied to an FF circuit positioned at the post stage of the corresponding FF circuit. A booby trap is realized by the two-input logic gates. The value input to each of the FF circuits is determined by logical operation of at most two logical values, so that the counter circuit can be adapted to the increasing frequency of a clock signal CLK. Thus, the counter circuit with the booby trap, capable of performing high-speed operation can be provided.

Abstract: A clock extraction circuit includes an edge detection unit for detecting a phase at which a trailing edge or a leading edge of input data is coincided with each other, and a phase judgement unit for comparing an edge position of the detected input data and a position of an input clock and for putting a weight, wherein the weight is put so that a shifting amount of the input clock is varied depending on a difference between the edge position of the input data and the position of the input clock.

Abstract: A scrambler includes m serial-connected registers with reset terminals, m exclusive OR gates, and m−1 switches turned on/off according to a generating polynomial. Transmission data is input to the first exclusive OR gate. The output of the first exclusive OR gate is input to the first register. The output of the i-th register is input to the (i+1)th exclusive OR gate via the i-th switch. The output of the (i+1)th exclusive OR gate is input to the i-th exclusive OR gate. The output of the m-th register is input to the m-th exclusive OR gate. In a bypass mode of transmission data, the m registers are reset. Since reception data is directly output from the first exclusive OR gate in the bypass mode of transmission data, it is possible to confirm whether data prior to the scramble process is correct or not.

Abstract: A counter circuit includes a plurality of flip flop circuits (FF circuits) sequentially connected for receiving a common clock signal, and two-input logic gates each having an input connected to an output of a corresponding FF circuit and the other input connected to an output of a common FF circuit, and of which output signal is supplied to an FF circuit positioned at the post stage of the corresponding FF circuit. A booby trap is realized by the two-input logic gates. The value input to each of the FF circuits is determined by logical operation of at most two logical values, so that the counter circuit can be adapted to the increasing frequency of a clock signal CLK. Thus, the counter circuit with the booby trap, capable of performing high-speed operation can be provided.

Abstract: A reset circuit outputting a reset signal /RESET when detecting an abnormal state in a ring counter is provided. The reset circuit divides the outputs of flip-flops constituting the ring counter into two groups, and check if either of the groups has “H” data. When “H” data exists in both of the two groups or when “H” data does not exist in either of the two groups, the reset circuit activates the reset signal /RESET to L level. Therefore, a semiconductor device can detect an erroneous state and recover to a normal state quickly.

Abstract: A reset circuit outputting a reset signal /RESET when detecting an abnormal state in a ring counter is provided. The reset circuit divides the outputs of flip-flops constituting the ring counter into two groups, and check if either of the groups has “H” data When “H” data exists in both of the two groups or when “H” data does not exist in either of the two groups, the reset circuit activates the reset signal /RESET to L level. Therefore, a semiconductor device can detect an erroneous state and recover to a normal state quickly.

Abstract: A digital data transmission system for transmitting digital data, a frame pulse signal, and a clock using a required minimum number of signal lines and with a simple circuit structure is provided. A signal separation circuit (46) that receives a multiple clock (CKFP) which is a frame pulse signal (FP) multiplexed with a clock (CK) includes a clock recovery circuit (47) for reproducing a recovered clock (RCK) by synchronization with the multiple clock (CKFP) using a synchronization loop, and a frame pulse signal separation circuit (48) for separating a recovered frame pulse signal (RFP) from the multiple clock (CKFP) on the basis of the recovered clock (RCK).

Abstract: A hold circuit holds results of processing in an arithmetic circuit collectively receiving four bits from inputs. The inventive arithmetic unit collectively processes an input data string, which has generally been processed bit by bit, by four bits at a time, whereby a CRC arithmetic operation can be speeded up. More preferably, the arithmetic unit can flexibly deal with change of a generating polynominal set in the arithmetic circuit when rendering set data corresponding to the generating polynomial changeable.

Abstract: A network communication device which can discard invalid packets at once is obtained. A plurality of cells received from input lines (IN#1-4) are stored in a shared buffer memory (SBM) and a control portion (CTL) manages tags and addresses. Among the received cells stored in the shared buffer memory (SBM), ones corresponding to discarded management data are not identified. Accordingly, virtually, the received cells in the shared buffer memory (SBM) can be discarded at once.

Abstract: The operating speed of an apparatus which operates with a clock is increased by obtaining a clock having a constant duty ratio. The maximum variable delay quantity of a first variable delay circuit 11 is set more than one cycle and less than two cycles of an input clock IN. The delay quantities of the first and second variable delay circuits 11, 12 are decreased with a control signal Vin. In addition, the ratio of the delay quantity of the second variable delay circuit 12 to that of the first variable delay circuit 11 is set to a constant value which is less than 1. A control portion 13 increases and decreases the control signal Vin in such a manner that the phases of an input clock IN and an output clock OUT-A of the first variable delay circuit are coincident with each other. An output clock OUT of the device is set by the output clock OUT-A of the first variable delay circuit, and is reset by an output clock OUT-B of the second variable delay circuit.

Abstract: A voltage applying means applies a voltage which determines the logical value of a node to the node, with the signal at the node fixed. Then, an applied voltage removing means removes the voltage applied by the voltage applying means. First and second detecting means detects the logical value of the node before and after the voltage application and removal of the applied voltage. A judging means compares the results of detection of the first and second detecting means to judge whether or not the node is at a high impedance.

Abstract: Flows of data are controlled using an externally supplied clock. A clock-synchronized C-element C1 outputs a sending signal S1 of H level to a data latch DL1 and the subsequent clock-synchronized C-element C2 and outputs an acknowledge signal A1 of H level, in synchronization with a rise of a clock signal CLK1 which is inputted to the clock-synchronized C-element C1 after the clock-synchronized C-element C1 receives a sending signal S0 of H level. Following this, the clock-synchronized C-element C1 causes the acknowledge signal A1 to fall by the next rise of the clock signal CLK1. This latches the data latch DL1. A clock signal CLK2 rises before the clock signal CLK1 falls and rises once again. In synchronization with this rise, the clock-synchronized C-element C2 performs a similar operation. As a result, the precedent clock-synchronized C-element C1 causes the sending signal S1 to fall.

Abstract: A plurality of shift memories shifting data are connected in series, destination indicating bits indicative of data destination are stored in destination indicating bit memories corresponding to the shift memories respectively, and a searching circuit is provided adjacent to each of the destination indicating bit memories, which searching circuit searches data by searching the destination indicating bits.