Abstract: Booster circuit comprising: first transistor that is connected to first node; capacitor that has one end connected to first node, and that is charged with voltage of first node when first transistor is activated; and control signal generating circuit that provides control terminal of first transistor with control signal being in accordance with first clock, wherein when first transistor is de-activated, capacitor boosts voltage of first node to first voltage by voltage being applied to or end of capacitor, voltage applied to or end being at least ½ as great as first supply voltage, and control signal generating circuit sets voltage of control signal when first transistor is de-activated to be first voltage of first node, and sets voltage of control signal when first transistor is activated to be voltage, difference between voltage and first voltage being equal to or smaller than value of first supply voltage.

Abstract: A nonvolatile memory device includes a memory cell that stores data by presence or absence of electrons accumulated in a floating gate, a read reference current generator that generates a read reference current for reading data from the memory cell based on a constant current from a constant current generator included therein, and a read voltage generator that generates a read voltage to be applied to a control gate of the memory cell during data reading. The read reference current generator generates a monitor voltage that varies according to variation of the read reference current and a threshold voltage of the memory cell. The read voltage generator generates the read voltage based on the monitor voltage.

Abstract: A nonvolatile semiconductor memory includes a memory cell, a first gate control circuit that is coupled to the memory cell, and a second gate control circuit that is coupled to the memory cell. The memory cell includes a first gate electrode that is formed above a channel region in a semiconductor substrate, a second gate electrode that is formed beside the first gate electrode, and that is capacitively coupled with the first gate electrode through a first insulating layer, and a charge trapping layer that is formed between the channel region and the second gate electrode, and that includes a second insulating layer for trapping a charge. Data stored in a memory cell transistor including the second gate electrode changes depending on an amount of the charge trapped in the charge trapping layer. The first gate control circuit applies a potential to the first gate electrode, when reading the data stored in the memory cell transistor.

Abstract: Booster circuit comprising: first transistor that is connected to first node; capacitor that has one end connected to first node, and that is charged with voltage of first node when first transistor is activated; and control signal generating circuit that provides control terminal of first transistor with control signal being in accordance with first clock, wherein when first transistor is de-activated, capacitor boosts voltage of first node to first voltage by voltage being applied to or end of capacitor, voltage applied to or end being at least ½ as great as first supply voltage, and control signal generating circuit sets voltage of control signal when first transistor is de-activated to be first voltage of first node, and sets voltage of control signal when first transistor is activated to be voltage, difference between voltage and first voltage being equal to or smaller than value of first supply voltage.

Abstract: A nonvolatile memory device includes a memory cell that stores data by presence or absence of electrons accumulated in a floating gate, a read reference current generator that generates a read reference current for reading data from the memory cell based on a constant current from a constant current generator included therein, and a read voltage generator that generates a read voltage to be applied to a control gate of the memory cell during data reading. The read reference current generator generates a monitor voltage that varies according to variation of the read reference current and a threshold voltage of the memory cell. The read voltage generator generates the read voltage based on the monitor voltage.

Abstract: A nonvolatile semiconductor memory includes a memory cell, a first gate control circuit that is coupled to the memory cell, and a second gate control circuit that is coupled to the memory cell. The memory cell includes a first gate electrode that is formed above a channel region in a semiconductor substrate, a second gate electrode that is formed beside the first gate electrode, and that is capacitively coupled with the first gate electrode through a first insulating layer, and a charge trapping layer that is formed between the channel region and the second gate electrode, and that includes a second insulating layer for trapping a charge. Data stored in a memory cell transistor including the second gate electrode changes depending on an amount of the charge trapped in the charge trapping layer. The first gate control circuit applies a potential to the first gate electrode, when reading the data stored in the memory cell transistor.

Abstract: A non-volatile memory device comprises a plurality of bit lines extending in a first direction, a plurality of word lines extending in a second direction substantially perpendicular to the first direction, a plurality of memory cells provided respectively so as to correspond to the positions of the intersections between the plurality of bit lines and the plurality of word lines, a plurality of source lines corresponding to a plurality of memory cells which are connected to a same bit line, a current source capable of supplying the constant current to a selected memory cell and the corresponding bit line and a voltage control circuit which keeps a voltage of a selected bit line equal to or higher than a predetermined voltage.

Abstract: In a nonvolatile semiconductor memory device, a semiconductor substrate has trenches formed to extend in parallel. A first electrode formed on the semiconductor substrate through an insulating film in each of the trenches, and a second electrode is formed on the first electrodes and the semiconductor substrate through the insulating film. A diffusion layer is formed in a predetermined depth of the semiconductor substrate in association with each of the trenches, and a trap film as a part of the insulating film configured to trap electric charge. A channel region is formed between adjacent two of the diffusion layers without any diffusion layer.

Abstract: A non-volatile memory device comprises a plurality of bit lines extending in a first direction, a plurality of word lines extending in a second direction substantially perpendicular to the first direction, a plurality of memory cells provided respectively so as to correspond to the positions of the intersections between the plurality of bit lines and the plurality of word lines, a plurality of source lines corresponding to a plurality of memory cells which are connected to a same bit line, a current source capable of supplying the constant current to a selected memory cell and the corresponding bit line and a voltage control circuit which keeps a voltage of a selected bit line equal to or higher than a predetermined voltage.

Abstract: A non-volatile semiconductor memory device being able to read, write and erase data at a much higher speed. The non-volatile semiconductor memory device used as a flash memory is composed of a memory cell array, a row address buffer, a row decoder, a row driver, a column address buffer, a column decoder, a column selector, a sense amplifier circuit, a writing circuit and a control circuit, wherein selection and non-selection of memory cells at the time of reading is performed not by a control gate of a memory transistor but by control on normal voltage of a switch transistor.

Abstract: A read only memory device memorizes data bits by selectively providing current paths of n-channel enhancement type memory transistors between digit lines and a ground voltage line, and one of the digit lines is coupled through an n-channel enhancement type transfer transistor of a column selector unit with a drain node of a charging transistor responsive to a control signal, wherein the charging transistor is implemented by an n-channel enhancement type field effect transistor so that the drain node thereof is balanced with the selected digit line upon completion of a precharging phase, thereby preventing an output inverting circuit coupled therewith from malfunction due to noise on the selected digit line.

Abstract: For implementation typically as an IC, a semiconductor decoding device comprises an additional MOS FET (26) of a first conductivity type between ground and output terminals, each (12) of which is connected to a power supply terminal (19) through a load MOS FET (18) of a second conductivity type and to a parallel circuit (13) of a plurality of MOS FET's (14-1etc) of the first conductivity type. Connected to the additional MOS FET and such load MOS FET's and supplied with a control input signal, a charge control section (27) puts the additional MOS FET in a conductive and a non-conductive state while putting each load MOS FET in an off and an on state. Preferably, a current limiting MOS FET (28) of the second conductivity type is connected between the supply terminal and the load MOS FET's and to a current limiting circuit (31-33) for limiting a load current which flows through the current limiting MOS FET and each load MOS FET put in the on state.

Abstract: A tri-state output buffer has a signal input terminal, a control terminal and a signal ouput terminal and is controlled by a control signal applied to the control terminal so as to be selectively put in an inactive condition maintaining the signal output terminal in a high impedance condition and in an active condition bringing the signal output terminal either into a high level or into a low level in response to a signal applied to the signal input terminal. The tri-state output buffer comprises a pre-buffer circuit having an input node connected to the signal input terminal, and an output node, and controlled by the control signal applied to the control terminal so as to selectively bring the output node into a high impedance condition or into an active condition assuming either a high level or a low level in response to the signal applied to the signal input terminal.

Abstract: A semiconductor memory device according to the present invention has a plurality of memory cells, a pair of data lines propagating the data bit, a data transfer unit responsive to address bits and operative to read out the data bit from one of the memory cells for providing the difference in voltage level between the data lines, a sense amplifier circuit having a pair of nodes and operative to increase the difference in voltage level by discharging one of the nodes, and a blocking circuit coupled between the data lines and the nodes and operative to relay the difference in voltage level between the data lines to said nodes, respectively, and the blocking circuit is further operative to isolate one of the nodes from associated data line when the node is discharged, so that the capacitive load applied to the sense amplifier circuit is drastically decreased so as to speed up the read-out operation.

Abstract: For decreasing the number of component transistors, a decoder buffer circuit has a first gate transistor activated on the selection of the two word lines associated thereto for an establishment of a current path, first and second complementary inverter circuits operative to complementarily activate one of the two word lines with a current fed from the current path depending upon the leaest significant bit of a row address signal, and a second gate transistor operative to isolate the two word lines from each other during the operation of the first and second complementary inverter circuits and to ground the two word lines outside the operation, so that the decoder buffer circuit is formed by only six component transistors for complementary activation of the two word lines.

Abstract: A programmable logic array has an interfacial plane between an AND plane and an OR plane for relaying the result of the AND operation to the OR plane, and the interfacial plane has intermediate nodes for the relaying functions which are simultaneously charged up to a high voltage level and selectively discharged to a low voltage level depending upon the result of the AND operation, wherein field effect transistors are provided for the selective discharging operation and simultaneously gated by a control signal line, so that only the gate capacitances of the field effect transistors are coupled to the control signal line, thereby improving the operation speed of the programmable logic array.

Abstract: A programmable logic array (PLA) circuit includes a product term array and a sum term array. The product term array is coupled to the sum term array via a control transistor. A gate electrode of the control transistor is coupled to an output of the product term array, and a source (or drain) electrode is coupled to an input end of the sum term array. A drain (or source) electrode of the control transistor is coupled to a power source. N-channel type transistors are employed in the product term and the sum term arrays, while a P-channel type transistor is employed as the control transistor.