Patents by Inventor Masahiko Kawata
Masahiko Kawata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5668402Abstract: A semiconductor device comprises a semiconductor substrate formed by a first single crystalline semiconductor material and semiconductor layers formed on the semiconductor substrate by a second single crystalline semiconductor material doped with an element which can easily surface segregate. The surface of the semiconductor substrate is formed of a crystalline plane substantially equivalent to a facet plane which is formed on the surface of the second single crystalline semiconductor material if the second single crystalline semiconductor material is epitaxially grown with being doped with the element on a (100) plane of the first single crystalline semiconductor material.Type: GrantFiled: May 24, 1993Date of Patent: September 16, 1997Assignee: Hitachi, Ltd.Inventors: Kazuhiro Mochizuki, Shigeo Goto, Chushirou Kusano, Masahiko Kawata, Hiroshi Masuda, Katsuhiko Mitani, Susumu Takahashi
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Patent number: 5381027Abstract: This invention discloses a heterojunction type field effect transistor such as 2DEG-FET and a heterojunction type bipolar transistor such as 2DEG-HBT. The former is fabricated by applying to the formation of its source and drain regions a technique which causes the disorder of the heterojunction by intoduction of an impurity such as by ion implantation or a technique which causes the disorder of the heterojunction by forming a film made of at least one kind of material selected from insulators, metals and semiconductors which have a different linear coefficient of thermal expansion from that of the material of a semiconductor substrate on the heterojunction semiconductor region which is to be disordered. The latter is fabricated by applying either of the techniques described above to a base ohmic contact region. These semiconductor devices can reduce the source-gate resistance and the parasitic base resistance.Type: GrantFiled: October 12, 1993Date of Patent: January 10, 1995Assignee: Hitachi, Ltd.Inventors: Toshiyuki Usagawa, Kenji Hiruma, Masahiko Kawata, Shigeo Goto, Katsuhiko Mitani, Masao Yamane, Susumu Takahashi, Tomonori Tanoue, Yoshinori Imamura
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Patent number: 5296733Abstract: A hetero junction bipolar transistor provides a contact area an area between an emitter (or collector) electrode and a wiring formed on the electrode that is larger than that of the emitter (or collector). A variation in voltage applied to an emitter (or collector)-base junctions is prevented and a stable operation of the transistor is attained. In addition, when an etching operation is carried out, an insulation film is formed on a side part of a mask. A patterning of the emitter (or collector) is then carried out and thus an emitter (or collector) having a size approximate to that of the mask is formed.Type: GrantFiled: November 19, 1990Date of Patent: March 22, 1994Assignee: Hitachi, Ltd.Inventors: Chushiroh Kusano, Hiroshi Masuda, Katsuhiko Mitani, Kazuhiro Mochizuki, Masaru Miyazaki, Masahiko Kawata, Susumu Takahashi
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Patent number: 5258631Abstract: This invention discloses a heterojunction type field effect transistor such as 2DEG-FET and a heterojunction type bipolar transistor such as 2DEG-HBT. The former is fabricated by applying to the formation of its source and drain regions a technique which causes the disorder of the heterojunction by introduction of an impurity such as by ion implantation or a technique which causes the disorder of the heterojunction by forming a film made of at least one kind of material selected from insulators, metals and semiconductors which have a different linear coefficient of thermal expansion from that of the material of a semiconductor substrate on the heterojunction semiconductor region which is to be disordered. The latter is fabricated by applying either of the techniques described above to a base ohmic contact region. These semiconductor devices can reduce the source-gate resistance and the parasitic base resistance.Type: GrantFiled: May 18, 1992Date of Patent: November 2, 1993Assignee: Hitachi, Ltd.Inventors: Toshiyuki Usagawa, Kenji Hiruma, Masahiko Kawata, Shigeo Goto, Katsuhiko Mitani, Masao Yamane, Susumu Takahashi, Tomonori Tanoue, Yoshinori Imamura
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Patent number: 5025751Abstract: A solid film forming apparatus, e.g., an MO-MBE (Metal-Organic Molecular Beam Epitaxy) apparatus, wherein evacuatable containers isolated from a growth chamber by a switching device and connected to raw material gas introduction pipings are provided between the growth chamber for a solid film, e.g., a compound semiconductor, and raw material gas introduction pipings. Growth of the solid film is controlled by opening and closing the switching device and evacuating the container at least while the switching device is closed during the growth of the solid film. An undesired influence on the growing film due to residual gas in the containers which are not used for growth can be prevented and, hence, interception and introduction of the raw material gas into the growth chamber can be performed with remarkably high controllability, and films of superior abruptness of the interface between films, e.g., the heterojunction of the compound semiconductor, can be obtained.Type: GrantFiled: June 14, 1989Date of Patent: June 25, 1991Assignee: Hitachi, Ltd.Inventors: Shinichiro Takatani, Shigeo Goto, Masahiko Kawata, Kenji Hiruma
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Patent number: 4740819Abstract: Disclosed is a photo-detective semiconductor device having, on a predetermined semiconductor substrate, at least a first semiconductor layer which exhibits a first conductivity type, a second semiconductor layer which is disposed on said first semiconductor layer, which has a forbidden band gap greater than that of said first semiconductor layer and which exhibits the first conductivity type, and a p-n junction which is formed by a region disposed in said second semiconductor layer and exhibiting a second conductivity type; characterized by comprising a third semiconductor layer which is disposed on said second semiconductor layer, which exhibits the first conductivity type and which has a surface protective function. The third semiconductor layer is usually made of a group III-V compound semiconductor of a quaternary system.Type: GrantFiled: June 30, 1986Date of Patent: April 26, 1988Assignee: Hitachi, Ltd.Inventors: Hirobumi Ouchi, Hiroshi Matsuda, Makoto Morioka, Masahiko Kawata, Kazuhiro Kurata, Yasushi Koga
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Patent number: 4212021Abstract: In a prior-art injection type light emitting device which is constructed so that a predetermined range of a p-n junction formed by a semiconductor substrate and an epitaxial layer provided thereon may radiate, a radiation region in the p-n junction becomes larger in area than the region into which current is introduced, on account of the current spreading phenomenon. The construction of a light emitting device free from the phenomenon and a method for manufacturing the light emitting device are disclosed.Type: GrantFiled: May 22, 1979Date of Patent: July 8, 1980Assignee: Hitachi, Ltd.Inventors: Yuichi Ono, Mitsuhiro Mori, Makoto Morioka, Kazuhiro Ito, Masahiko Kawata, Kazuhiro Kurata
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Patent number: 4122486Abstract: A light emitting element made of a group III - V compound semiconductor has a p-n junction and a hetero-junction which are identical; the mixing ratio (band gap) of a p-type layer on the light emitting side is sufficiently smaller than that of an n-type layer on the opposite side. The semiconductor light-emitting element is especially useful as a light source, for optical communications, photoexcitation, etc.Type: GrantFiled: February 24, 1977Date of Patent: October 24, 1978Assignee: Hitachi, Ltd.Inventors: Yuichi Ono, Makoto Morioka, Kazuhiro Ito, Mitsuhiro Mori, Masahiko Kawata, Kazuhiro Kurata