Patents by Inventor Masahiko KIJIMA

Masahiko KIJIMA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240101899
    Abstract: To provide a semiconductor light emitting device which is capable of accomplishing a broad color reproducibility for an entire image without losing brightness of the entire image. A light source provided on a backlight for a color image display device has a semiconductor light emitting device comprising a solid light emitting device to emit light in a blue or deep blue region or in an ultraviolet region and phosphors, in combination. The phosphors comprise a green emitting phosphor and a red emitting phosphor. The green emitting phosphor and the red emitting phosphor are ones, of which the rate of change of the emission peak intensity at 100° C. to the emission intensity at 25° C., when the wavelength of the excitation light is 400 nm or 455 nm, is at most 40%.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 28, 2024
    Applicants: CITIZEN ELECTRONICS CO., LTD., NICHIA CORPORATION
    Inventors: Byungchul HONG, Naoki SAKO, Naoto KIJIMA, Masahiko YOSHINO, Takashi HASE, Fumiko YOYASU, Kentarou HORIBE
  • Patent number: 11516911
    Abstract: A glass circuit board includes, on a glass substrate, a stress relief layer, a seed layer, and an electroplated layer including copper plating. The stress relief layer is an insulator formed by dry coating method and applies a compressive residual stress to the glass substrate at room temperature. The stress relief layer thus reduces cracking, fracturing or warpage of the glass substrate caused by thermal expansion and shrinkage of the copper plating due to heating and cooling of the glass circuit board during manufacturing or thermal cycling, ensuring high connection reliability of the glass circuit board.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: November 29, 2022
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventor: Masahiko Kijima
  • Publication number: 20210076491
    Abstract: A glass circuit board includes, on a glass substrate, a stress relief layer, a seed layer, and an electroplated layer including copper plating. The stress relief layer is an insulator formed by dry coating method and applies a compressive residual stress to the glass substrate at room temperature. The stress relief layer thus reduces cracking, fracturing or warpage of the glass substrate caused by thermal expansion and shrinkage of the copper plating due to heating and cooling of the glass circuit board during manufacturing or thermal cycling, ensuring high connection reliability of the glass circuit board.
    Type: Application
    Filed: November 23, 2020
    Publication date: March 11, 2021
    Applicant: TOPPAN PRINTING CO.,LTD.
    Inventor: Masahiko KIJIMA