Abstract: A current detection circuit that can normally perform a current detection operation to detect a current in a memory cell of a memory device even if an applied power supply voltage is a low voltage, includes a current detection means which comprises first and second MOS transistors of a same channel type and third to sixth MOS transistors of a channel type different from the channel type of the first and second MOS transistors, and a MOS gate control means which supplies, to a control electrode of each of the first and second MOS transistors, a voltage which is obtained by subtracting an absolute value of a threshold voltage of each of the first and second MOS transistors from the power supply voltage when the power supply voltage is equal to or lower than the absolute value of the threshold voltage.

Abstract: A current detection circuit that can normally perform a current detection operation to detect a current in a memory cell of a memory device even if an applied power supply voltage is a low voltage, includes a current detection means which comprises first and second MOS transistors of a same channel type and third to sixth MOS transistors of a channel type different from the channel type of the first and second MOS transistors, and a MOS gate control means which supplies, to a control electrode of each of the first and second MOS transistors, a voltage which is obtained by subtracting an absolute value of a threshold voltage of each of the first and second MOS transistors from the power supply voltage when the power supply voltage is equal to or lower than the absolute value of the threshold voltage.

Abstract: A semiconductor memory device includes word lines, drain lines, source lines, a memory array including plural memory cells formed from a field effect transistor, a data write circuit, a write control circuit, and a word line drive circuit, wherein the write control circuit outputs the drain drive voltage of H-level to the selected memory cell when a data write operation is commanded, and outputs the drain drive voltage of L-level when a data write operation is not commanded, and the data write circuit generates a write voltage corresponding to a logical value of data to be written into the selected memory cell based on the drain drive voltage outputted from the write control circuit, and supplies the write voltage as the source drive voltage via the source line to the selected memory cell when a data write operation is commanded by the first control signal.

Abstract: A semiconductor memory device includes word lines, drain lines, source lines, a memory array including plural memory cells formed from a field effect transistor, a data write circuit, a write control circuit, and a word line drive circuit, wherein the write control circuit outputs the drain drive voltage of H-level to the selected memory cell when a data write operation is commanded, and outputs the drain drive voltage of L-level when a data write operation is not commanded, and the data write circuit generates a write voltage corresponding to a logical value of data to be written into the selected memory cell based on the drain drive voltage outputted from the write control circuit, and supplies the write voltage as the source drive voltage via the source line to the selected memory cell when a data write operation is commanded by the first control signal.

Abstract: There is provided a semiconductor memory device capable of eliminating the occurrence of delays in access when switching from a standby state to an active state. A drain voltage generator 10A generates a predetermined drain voltage MCD which is low in driving performance owing to PMOS 15, 17 and NMOS 16, 18 each having large ON resistance irrespective of the presence of a chip selection signal and apply the drain voltage to each of memory arrays. When read operation is started when a chip selection signal /CE goes “L”, the drain voltage MCD is generated by PMOSs 11, 15 and NMOSs 12 to 14 with a predetermined driving performance. As a result, a predetermined drain voltage MCD is always applied when switching from a standby state to an active state, thereby eliminating the occurrence of delays in access to a memory cell.

Abstract: There is provided a semiconductor memory device capable of eliminating the occurrence of delays in access when switching from a standby state to an active state. A drain voltage generator 10A generates a predetermined drain voltage MCD which is low in driving performance owing to PMOS15, 17 and NMOS16, 18 each having large ON resistance irrespective of the presence of a chip selection signal and apply the drain voltage to each of memory arrays. When read operation is started when a chip selection signal /CE goes “L”, the drain voltage MCD is generated by PMOSs 11, 15 and NMOSs 12 to 14 with a predetermined driving performance. As a result, a predetermined drain voltage MCD is always applied when switching from a standby state to an active state, thereby eliminating the occurrence of delays in access to a memory cell.

Abstract: When a data write into a memory cell 11 is completed and a reset signal RST is set to level “H,” a control voltage MCD output by a write control circuit 30 is set to a ground voltage GND to start a discharge of the electrical charge on the drain line DL. When a specific length of time has elapsed, a reset signal RST1 output by a delay circuit 50 is set to level “H,” and an output signal from a data write circuit 40 is set to the ground voltage GND to start a discharge of the electrical charge on a source line SL. Since the electrical discharge at the drain line DL starts earlier than the discharge of the source line, the difference in the potential between the drain and the source in the memory cell 11 during a reset operation does not increase, thereby ensuring that no electrical current flows to the memory cell 11. Consequently, an erroneous data write and a delay in access occurring due to an increase in the threshold voltage can be prevented.

Abstract: A constant voltage circuit is made up of a first transistor of an N-channel type having a drain connected to a power supply voltage and a source connected to the drain of the respective memory cells, a second transistor of an P-channel type having a source connected to the power supply voltage, a gate connected to a ground, and a drain connected to a gate of the first transistor, and a reference voltage generating circuit turning on and fixing the gate of the first transistor to the predetermined voltage when the power supply voltage is more than a predetermined voltage. Accordingly, the constant voltage circuit can apply a high voltage for the output voltage Vmcd to drains of each memory cells even if the power supply voltage Vcc is a low voltage and further can achieve the improvement of the access velocity for the data reading operation of the semiconductor memory device.

Abstract: A semiconductor memory circuit includes a memory cell subarray, a subarray driver and a cell drain potential generator. The memory cell subarray includes word lines, memory cell transistors and a cell drain line selection transistor. Each of the memory cell transistors has a gate connected to one of the word lines, a drain and a source. The cell drain line selection transistor has a first terminal connected to the drains of the memory cell transistors, a second terminal and a gate. The semiconductor memory circuit further has a subarray driver connected to the gate of the cell drain line selection transistor for applying a predetermined potential to the cell drain line selection transistor in response to a write control signal and an address signal, and a cell drain potential generator connected to the second terminal of the cell drain line selection transistor for providing a cell drain potential to the second terminal of the cell drain line selection transistor in response to the write control signal.

Abstract: A semiconductor memory device of the present invention comprises a memory cell array including row lines, column lines and memory cells arranged in rows and columns is disclosed. Each memory cell is connected to one of the row lines and one of the column lines. The semiconductor memory device further comprises a row select circuit connected to the row lines for selecting one of the row lines in response to a row select signal, a column select circuit connected to the column lines for selecting one of the column lines in response to a column select signal, a potential detector connected to the memory cell array for detecting a potential level of the lines of the memory cell array, and a test memory cell array connected to said potential detector through a test line. The test memory cell array tests a structural default of the row lines. The test memory cell array has a row of transistors each of which has a source connected to a potential source.