Patents by Inventor Masahiko Nakamae

Masahiko Nakamae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7977221
    Abstract: A strained Si—SOI substrate, and a method for producing the same are provided, wherein the method includes the steps of growing a SiGe mixed crystal layer 14 on an SOI substrate 10 having an Si layer 13 and a buried oxide film 12; forming protective films 15, 16 on the surface of the SiGe mixed crystal layer 14; implanting light element ions into a vicinity of the interface between the Si layer 13 and the buried oxide film 12; performing a first heat treatment at a temperature in the range of 400 to 1000° C.; performing a second heat treatment at a temperature not lower than 1050° C. under an oxidizing atmosphere; performing a third heat treatment at a temperature not lower than 1050° C. under an inert atmosphere; removing the Si oxide film 18 formed on the surface; and forming a strained Si layer 19.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: July 12, 2011
    Assignees: Sumco Corporation, Kyushu University, National University Corporation
    Inventors: Masaharu Ninomiya, Koji Matsumoto, Masahiko Nakamae, Masanobu Miyao
  • Patent number: 7767548
    Abstract: A method for manufacturing a semiconductor wafer with a strained Si layer having sufficient tensile strain and few crystal defects, while achieving a relatively simple layered structure, is provided.
    Type: Grant
    Filed: August 17, 2007
    Date of Patent: August 3, 2010
    Assignees: Sumco Corporation, Kyushu University, National University Corporation
    Inventors: Masaharu Ninomiya, Koji Matsumoto, Masahiko Nakamae, Masanobu Miyao, Taizoh Sadoh
  • Publication number: 20090090933
    Abstract: A strained Si-SOI substrate, and a method for producing the same are provided, wherein the method includes the steps of growing a SiGe mixed crystal layer 14 on an SOI substrate 10 having an Si layer 13 and a buried oxide film 12; forming protective films 15, 16 on the surface of the SiGe mixed crystal layer 14; implanting light element ions into a vicinity of the interface between the Si layer 13 and the buried oxide film 12; performing a first heat treatment at a temperature in the range of 400 to 1000° C.; performing a second heat treatment at a temperature not lower than 1050° C. under an oxidizing atmosphere; performing a third heat treatment at a temperature not lower than 1050° C. under an inert atmosphere; removing the Si oxide film 18 formed on the surface; and forming a strained Si layer 19.
    Type: Application
    Filed: October 5, 2007
    Publication date: April 9, 2009
    Applicants: Sumco Corporation, Kyushu University, National University Corporation
    Inventors: Masaharu Ninomiya, Koji Matsumoto, Masahiko Nakamae, Masanobu Miyao
  • Publication number: 20090047526
    Abstract: A method for manufacturing a semiconductor wafer with a strained Si layer having sufficient tensile strain and few crystal defects, while achieving a relatively simple layered structure, is provided.
    Type: Application
    Filed: August 17, 2007
    Publication date: February 19, 2009
    Inventors: Masaharu Ninomiya, Koji Matsumoto, Masahiko Nakamae, Masanobu Miyao, Taizoh Sadoh
  • Patent number: 7253082
    Abstract: A plurality of recessed portions having different depths is formed in a surface of the active layer wafer or in a bonding surface of the supporting substrate wafer. Those wafers are bonded to each other with an insulation film interposed therebetween. This allows a cavity of higher dimensional precision to be buried therein. A plurality of cavities may be formed simultaneously in a plurality of locations within the plane of the substrate, which allows the thickness of the SOI layer to be set arbitrarily. Accordingly, such a semiconductor device can be fabricated easily in which a MOS type element and a bipolar element are formed on the same chip in a mixed manner.
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: August 7, 2007
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Naoshi Adachi, Masahiko Nakamae
  • Publication number: 20060214257
    Abstract: A strained Si-SOI substrate is produced by a method comprising: growing a SiGe mixed crystal layer on an SOI substrate having a Si layer of not less than 5 nm in thickness and a buried oxide layer; forming a protective film on the SiGe mixed crystal layer; implanting light element ions into a vicinity of an interface between the silicon layer and the buried oxide layer; a first heat treatment for heat treating the substrate at a temperature of 400 to 1000° C. in an inert gas atmosphere; a second heat treatment for heat treating the substrate at a temperature not lower than 1050° C. in an oxidizing atmosphere containing chlorine; removing an oxide film from the surface of the substrate, and forming a strained silicon layer on the surface of the substrate.
    Type: Application
    Filed: March 23, 2006
    Publication date: September 28, 2006
    Inventors: Masaharu Ninomiya, Koji Matsumoto, Masahiko Nakamae, Masanobu Miyao
  • Publication number: 20050081958
    Abstract: A plurality of recessed portions having different depths is formed in a surface of the active layer wafer or in a bonding surface of the supporting substrate wafer. Those wafers are bonded to each other with an insulation film interposed therebetween. This allows a cavity of higher dimensional precision to be buried therein. A plurality of cavities may be formed simultaneously in a plurality of locations within the plane of the substrate, which allows the thickness of the SOI layer to be set arbitrarily. Accordingly, such a semiconductor device can be fabricated easily in which a MOS type element and a bipolar element are formed on the same chip in a mixed manner.
    Type: Application
    Filed: October 22, 2003
    Publication date: April 21, 2005
    Applicant: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Naoshi Adachi, Masahiko Nakamae
  • Patent number: 6372628
    Abstract: A structure and manufacturing process of a low dielectric constant interlayer insulating film used between wiring layers and semiconductor devices using such film are disclosed. The insulating film which can withstand in an actual process comprises an amorphous carbon fluoride film. A diamond like carbon film and a silicon excess layer are disposed on both sides of the amorphous carbon fluoride film to be inserted between the wiring layers, whereby adhesion to wiring and another insulating film contacting it is significantly enhanced. In addition, a silicon based insulating film is disposed and flattened on a multilayer film containing an amorphous carbon fluoride film buried with a wiring layer, and is used as a hard mask for anisotropically etching the diamond like carbon film and the amorphous carbon fluoride film with oxygen plasma to form a via hole.
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: April 16, 2002
    Assignee: NEC Corporation
    Inventors: Yoshihisa Matsubara, Ko Noguchi, Shinya Ito, Noriaki Oda, Akira Matsumoto, Takashi Ishigami, Masahiko Nakamae, Tadahiko Horiuchi, Kazuhiko Endo, Toru Tatsumi, Yoshishige Matsumoto
  • Patent number: 6091081
    Abstract: A structure and manufacturing process of a low dielectric constant interlayer insulating film used between wiring layers and semiconductor devices using such film are disclosed. The insulating film which can withstand in an actual process comprises an amorphous carbon fluoride film. A diamond like carbon film and a silicon excess layer are disposed on both sides of the amorphous carbon fluoride film to be inserted between the wiring layers, whereby adhesion to wiring and another insulating film contacting it is significantly enhanced. In addition, a silicon based insulating film is disposed and flattened on a multilayer film containing an amorphous carbon fluoride film buried with a wiring layer, and is used as a hard mask for anisotropically etching the diamond like carbon film and the amorphous carbon fluoride film with oxygen plasma to form a via hole.
    Type: Grant
    Filed: December 2, 1997
    Date of Patent: July 18, 2000
    Assignee: NEC Corporation
    Inventors: Yoshihisa Matsubara, Ko Noguchi, Shinya Ito, Noriaki Oda, Akira Matsumoto, Takashi Ishigami, Masahiko Nakamae, Tadahiko Horiuchi, Kazuhiko Endo, Toru Tatsumi, Yoshishige Matsumoto
  • Patent number: 5296391
    Abstract: A method of manufacturing a semiconductor device includes a monocrystalline semiconductor layer of one conductivity type with a first insulating film covering the semiconductor layer. An aperture is selectively formed in the first insulating film to expose a part of the semiconductor layer. A first polycrystalline semiconductor film of an opposite conductivity type is formed on the first insulating film and has an overhang portion projecting over the aperture from an edge of the first insulating film defining the aperture.
    Type: Grant
    Filed: May 26, 1993
    Date of Patent: March 22, 1994
    Assignee: NEC Corporation
    Inventors: Fumihiko Sato, Masahiko Nakamae, Mitsuhiro Sugiyama, Tsutomu Tashiro
  • Patent number: 4963957
    Abstract: A semiconductor device having a bipolar transistor with a trench is disclosed. An active region of the substrate is surrounded by the trench. Collector, base and emitter regions of the transistor are formed in the active region. A collector electrode is formed in a lower section of the trench, and a base electrode is formed in an upper section of the identical trench.
    Type: Grant
    Filed: September 29, 1988
    Date of Patent: October 16, 1990
    Assignee: NEC Corporation
    Inventors: Susumu Ohi, Masahiko Nakamae, Hiroshi Shiba
  • Patent number: 4800177
    Abstract: A process for making a semiconductor device including a semiconductor layer heavily doped to a predetermined dopant concentration and a multilayer contact system in contact with a surface portion of the heavily doped semiconductor layer, the multilayer contact system comprising a metal silicide layer of the silicide of a refractory metal, the metal silicide layer directly contacting the surface portion of the heavily doped semiconductor layer and being lower in dopant concentration than the predetermined dopant concentration of the semiconductor layer, a barrier layer of at least one metal on the metal silicide layer, and an electrode layer including a highly conductive metal on the barrier layer.
    Type: Grant
    Filed: March 14, 1986
    Date of Patent: January 24, 1989
    Assignee: NEC Corporation
    Inventor: Masahiko Nakamae
  • Patent number: 4191595
    Abstract: In a semiconductor device including at least one active semiconductor region isolated by an oxide layer in a semiconductor substrate having a principal surface, at least two PN junctions, terminating at the oxide layer, are formed in the active region, by introduction of impurities into the active region with the active region surface never exposed during their formation. The junctions may partly reach the principal surface. The impurities may be introduced by ion implantation through a thin oxide film overlying the active region, and through use of other films placed on the oxide film, or by the known melt-through technique. At least one junction may be formed by epitaxial growth of a semiconductor layer of the opposite conductivity type.
    Type: Grant
    Filed: September 21, 1977
    Date of Patent: March 4, 1980
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Kunio Aomura, Fujiki Tokuyoshi, Masahiko Nakamae