Abstract: An electronic component package includes an electronic component substrate disposed on a dice pad, a plurality of leads disposed around the dice pad, wires connecting the leads and signal pads of the electronic component substrate, and a molding resin for sealing the dice pad, the electronic component substrate, and the wires such that the bottom surfaces and one end surfaces of the leads are exposed, wherein the one end surfaces of the leads do not protrude out of the molding resin, and recessions that open at the one end surfaces are formed in the bottom surfaces of the leads.

Abstract: A field effect transistor includes a III-V compound semiconductor substrate having a surface, III-V compound semiconductor layers successively disposed on the surface, including, an InAlAs layer, an InP layer, and an InGaAs layer, a gate recess penetrating through the InGaAs layer and the InP layer, and a gate electrode in the gate recess in contact with the InAlAs layer. In this structure, the contact surface of the gate electrode with the InAlAs layer is coplanar with the interface between the InP layer and the InAlAs layer.

Abstract: A heterojunction bipolar transistor includes a III-V compound semiconductor substrate having a surface; III-V compound semiconductor layers successively disposed on the surface including an InGaAs layer, an InP layer, and an InAlAs layer; and base electrodes in contact with the InGaAs layer wherein contact of the base electrodes with the InGaAs layer is coplanar with contact between the InP layer and the InGaAs layer.