Abstract: According to one embodiment, a solid-state imaging device includes a signal level comparing circuit. The signal level comparing circuit compares the levels among the signals of first peripheral pixels, the levels among the signals of second peripheral pixels, the levels among the signals of third peripheral pixels. The first peripheral pixels are arranged with the pixels for colors other than the color for the target pixel interposed between the first peripheral pixels and the target pixel. The second peripheral pixels are disposed on extension lines in directions from the target pixel to the first peripheral pixels, and the third peripheral pixels are disposed between the second peripheral pixels.

Abstract: According to one embodiment, a solid-state imaging device includes a signal level comparing circuit. The signal level comparing circuit compares the levels among the signals of first peripheral pixels, the levels among the signals of second peripheral pixels, the levels among the signals of third peripheral pixels. The first peripheral pixels are arranged with the pixels for colors other than the color for the target pixel interposed between the first peripheral pixels and the target pixel. The second peripheral pixels are disposed on extension lines in directions from the target pixel to the first peripheral pixels, and the third peripheral pixels are disposed between the second peripheral pixels.

Abstract: According to the embodiment, a feedback clamp circuit is included, which increases or decreases a clamp parameter so that a black level approaches a target value while controlling a change amount of the clamp parameter, which sets the black level, based on the black level read out from OB pixels.

Abstract: According to one embodiment, a third optical black portion is arranged in parallel with a first optical black portion in a row direction and in parallel with a second optical black portion in column direction. At least one of the vertical line correction circuit and the horizontal line correction circuit adds/subtracts arithmetic average of the third black level signal generated by the third optical black portion.

Abstract: According to the embodiment, a feedback clamp circuit is included, which increases or decreases a clamp parameter so that a black level approaches a target value while controlling a change amount of the clamp parameter, which sets the black level, based on the black level read out from OB pixels.

Abstract: According to one embodiment, a third optical black portion is arranged in parallel with a first optical black portion in a row direction and in parallel with a second optical black portion in column direction. At least one of the vertical line correction circuit and the horizontal line correction circuit adds/subtracts arithmetic average of the third black level signal generated by the third optical black portion.

Abstract: An information device includes a personal information reception processing section which receives personal information read from a recording medium by using a predetermined information reader, and an inquiry request/result reception section which issues, to another information device through a network, a request for an identification inquiry regarding a person indicated by the personal information received by the personal information reception processing section, and receives and outputs an identification inquiry result returned in accordance with the request.

Abstract: A semiconductor device to which two kinds of electric voltage can be supplied comprises: a first MOS transistor formed in the first well having a first conduction type and being fixed to a first electric potential, a second MOS transistor formed in a second well having a second conduction type different from the first one and being fixed to a second electric potential higher than the first electric potential, and a third well formed between the first and second wells having the second conduction type and being fixed to a ground electric potential. The first MOS transistor comprises a first gate oxide film having a prescribed thickness and a first gate electrode having a prescribed gate length, while the second MOS transistor comprises a second gate oxide film having a thickness larger than the prescribed thickness of the first gate oxide film and a second gate electrode having a gate length longer than the prescribed thickness of the first gate length.

Abstract: The present invention relates to a bonding pad electrode structure having sufficiently large allowable current and improved to prevent generation of cracks in an interlayer insulating film by mechanical stress at the time of wire bonding. Interlayer insulating films are provided directly on a semiconductor substrate. An uppermost interconnection layer is provided on interlayer insulating films. Since a lower interconnection layer does not exist immediately below a portion of the uppermost interconnection layer used as a bonding pad, cracks are not generated in the interlayer insulating films at the time of wire bonding. Further, since the uppermost interconnection layer is connected to lower interconnection layers, the current entering the bonding pad is dispersed to these interconnection layers.