Abstract: This receiving apparatus achieves circuit size reduction and consumption power reduction, while still having an advantage of high-speed processing. In a receiving apparatus (100), a frequency component detector (105) has a Fourier conversion operation unit provided therein, and performs high-speed Fourier conversion with respect to digital signals outputted from an ADC (104), said high-speed Fourier conversion being performed within a range instructed by means of an operation range control unit (106), and the frequency component detector detects a plurality of frequency components (FFT signals) of the digital signals. The operation range control unit (106) sets, using the FFT signals outputted from the frequency component detector (105), the frequency range within which the Fourier conversion operation is to be performed, and instructs the range to the frequency component detector (105).

Abstract: This receiving apparatus achieves circuit size reduction and consumption power reduction, while still having an advantage of high-speed processing. In a receiving apparatus (100), a frequency component detector (105) has a Fourier conversion operation unit provided therein, and performs high-speed Fourier conversion with respect to digital signals outputted from an ADC (104), said high-speed Fourier conversion being performed within a range instructed by means of an operation range control unit (106), and the frequency component detector detects a plurality of frequency components (FFT signals) of the digital signals. The operation range control unit (106) sets, using the FFT signals outputted from the frequency component detector (105), the frequency range within which the Fourier conversion operation is to be performed, and instructs the range to the frequency component detector (105).

Abstract: A receiver simultaneously receives a plurality of signals on a plurality of channels, which have been modulated using frequency shift keying (FSK). A calculation range controller detects a Mark frequency and a Space frequency for each channel, determines for each channel a frequency range for Fourier transform calculation of the plurality of receiving signals, based on the detected Mark frequency and the detected Space frequency and indicates the frequency range to a frequency component detector. The frequency component detector performs Fourier transformation on the determined frequency range for each channel and detects, for each channel, frequency components (FFT signals) of the plurality of receiving signals respectively. The channel shifter allocates the FFT signals output from the frequency component detector to data of channel 1 to channel N and outputs the signals to respective demodulators.

Abstract: A receiver simultaneously receives a plurality of signals on a plurality of channels, which have been modulated using frequency shift keying (FSK). A calculation range controller detects a Mark frequency and a Space frequency for each channel, determines for each channel a frequency range for Fourier transform calculation of the plurality of receiving signals, based on the detected Mark frequency and the detected Space frequency and indicates the frequency range to a frequency component detector. The frequency component detector performs Fourier transformation on the determined frequency range for each channel and detects, for each channel, frequency components (FFT signals) of the plurality of receiving signals respectively. The channel shifter allocates the FFT signals output from the frequency component detector to data of channel 1 to channel N and outputs the signals to respective demodulators.

Abstract: A frequency range for Fourier transform is controlled and a digital signal is subjected to fast Fourier transform within the controlled range, whereby a plurality of frequency components (FFT signals) in the digital signal are detected. A transmission rate of a received signal is determined using the detected FFT signals and the FFT signals are demodulated by an operation at a speed corresponding to the determined transmission rate.

Abstract: A clock signal generation apparatus containing variable delay devices for varying the delay time of two-phase clock signals used in a load circuit that uses non-overlap clock signals; a non-overlap detector for detecting a non-overlap time in the H-level zones of the two-phase clock signals and outputting a detection signal corresponding to the non-overlap time; and a control signal generation section for generating a control signal that is used to control the variable delay devices on the basis of the detection signal from the non-overlap detector, and capable of securely generating the two-phase clock signals having an optimal non-overlap time while absorbing fluctuations due to temperature characteristics, power supply voltage characteristics and individual differences in components.

Abstract: A multibit quantizer is provided, at its input terminals, with a variable gain circuit and an offset addition circuit to perform tracking control in which for each sampling time, the level of an offset signal of the offset addition circuit is adjusted based on output digital data of an output processing circuit and the preceding control signal of an offset control circuit so that the quantizer operates without causing a saturation operation. As a result, the output digital data, in which the number of bits is greater than the number of bits of the quantizer by the offset value controlled by the offset addition circuit, is outputted from the output processing circuit for each sampling time.

Abstract: A multibit quantizer is provided, at its input terminals, with a variable gain circuit and an offset addition circuit to perform tracking control in which for each sampling time, the level of an offset signal of the offset addition circuit is adjusted based on output digital data of an output processing circuit and the preceding control signal of an offset control circuit so that the quantizer operates without causing a saturation operation. As a result, the output digital data, in which the number of bits is greater than the number of bits of the quantizer by the offset value controlled by the offset addition circuit, is outputted from the output processing circuit for each sampling time.

Abstract: A modulator, and more particularly an HPSK modulator, is disclosed that enables the circuit scale to be reduced and also enables power consumption to be reduced. An HPSK modulator 209 incorporated in a radio communication apparatus or the like is equipped with a spreading code multiplication section 11, a complex arithmetic section 101, a coefficient determination section 51, and raised COS filters 41 and 42. Spreading code multiplication section 11 multiplies transmit data DPDCH1 by a spreading code Cd1. Complex arithmetic section 101 performs complex arithmetic on an output signal output from spreading code multiplication section 11 and a scrambling code Sn, and performs conversion to complex data. Coefficient determination section 51 determines a filter coefficient Ad1n based on a gain factor ?d1 that determines transmission power. Raised COS filters 41 and 42 band-limit the complex data using the filter coefficient.

Abstract: In a clock signal generation apparatus, a clock signal delay calculation section has a delay detection circuit for monitoring the delay characteristics of the variable delay circuits of a clock signal generation circuit due to external variation factors and calculates the delay amounts of N-phase clock signals, and a clock signal delay control section varies the delay amounts of the variable delay circuits on the basis of delay variation data, external variation factors being used as parameters thereof, stored in a delay variation data section and the calculated delay amounts of the N-phase clock signals. In the case that, for example, clock signals required for a discrete-time circuit have changed due to external variation factors, such as power supply voltage and environmental temperature, the non-overlap times and the duty ratios of the clock signals required for the discrete-time circuit can be set to optimal values.

Abstract: A clock signal generation apparatus containing variable delay devices for varying the delay time of two-phase clock signals used in a load circuit that uses non-overlap clock signals; a non-overlap detector for detecting a non-overlap time in the H-level zones of the two-phase clock signals and outputting a detection signal corresponding to the non-overlap time; and a control signal generation section for generating a control signal that is used to control the variable delay devices on the basis of the detection signal from the non-overlap detector, and capable of securely generating the two-phase clock signals having an optimal non-overlap time while absorbing fluctuations due to temperature characteristics, power supply voltage characteristics and individual differences in components.

Abstract: In a delta-sigma modulator including first and second subtractors, first and second integrators, a quantizer, and a DA converter, a first feedback circuit includes first charge holding circuits which hold charges of the analog signal from the DA converter for different sampling intervals, can change a feedback amount of the analog signal from the DA converter, and outputs the analog signal from each first charge holding circuits to the second subtractor. A second feedback circuit includes second charge holding circuits which hold charges of the analog signal from the second integrator for different sampling intervals, can change a feedback amount of the analog signal from the second integrator, and outputs an analog signal from each of the second charge holding circuits to the second subtractor. A controller switches an order of filter characteristic of the delta sigma modulator by changing feedback amounts of the first and second feedback circuits.

Abstract: An A/D converter that supports multi-mode and that can minimize power consumption is provided. A hybrid A/D converter comprises: hybrid stages composed of 1.5-bit A/D converter for pipeline use that convert analogue input signals into digital signals; 1/1.5-bit D/A converters that switch between pipeline use and delta-sigma modulation use according to the mode in use; analogue adders that subtract output of the 1/1.5 D/A converters from the analogue input signals; and analogue operation circuits that receive as input the output of the analogue adders and function as amplifiers in pipeline mode and as integrators in delta-sigma mode.

Abstract: In a delta-sigma modulator including first and second subtractors, first and second integrators, a quantizer, and a DA converter, a first feedback circuit includes first charge holding circuits which hold charges of the analog signal from the DA converter for different sampling intervals, can change a feedback amount of the analog signal from the DA converter, and outputs the analog signal from each first charge holding circuits to the second subtractor. A second feedback circuit includes second charge holding circuits which hold charges of the analog signal from the second integrator for different sampling intervals, can change a feedback amount of the analog signal from the second integrator, and outputs an analog signal from each of the second charge holding circuits to the second subtractor. A controller switches an order of filter characteristic of the delta sigma modulator by changing feedback amounts of the first and second feedback circuits.

Abstract: An A/D converter that supports multi-mode and that can minimize power consumption is provided. A hybrid A/D converter 100 comprises: hybrid stages 101 to 103 composed of 1.5-bit A/D converter 111, 121 and 131 for pipeline use that convert analogue input signals into digital signals; 1/1.5-bit D/A converters 112, 122 and 132 that switch between pipeline use and delta-sigma modulation use according to the mode in use; analogue adders 113, 123 and 133 that subtract output of the 1/1.5 D/A converters 112, 122 and 132 from the analogue input signals; and analogue operation circuits 114, 124 and 134 that receive as input the output of the analogue adders 113, 123 and 133 and function as amplifiers in pipeline mode and as integrators in delta-sigma mode.

Abstract: A modulator, and more particularly an HPSK modulator, is disclosed that enables the circuit scale to be reduced and also enables power consumption to be reduced. An HPSK modulator 209 incorporated in a radio communication apparatus or the like is equipped with a spreading code multiplication section 11, a complex arithmetic section 101, a coefficient determination section 51, and raised COS filters 41 and 42. Spreading code multiplication section 11 multiplies transmit data DPDCH1 by a spreading code Cd1. Complex arithmetic section 101 performs complex arithmetic on an output signal output from spreading code multiplication section 11 and a scrambling code Sn, and performs conversion to complex data. Coefficient determination section 51 determines a filter coefficient Ad1n based on a gain factor ?d1 that determines transmission power. Raised COS filters 41 and 42 band-limit the complex data using the filter coefficient.